Datasheet 74F125SJX, 74F125SJ, 74F125SCX, 74F125SC, 74F125PC Datasheet (Fairchild Semiconductor)

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© 1999 Fairchild Semiconductor Corporation DS009475 www.fairchildsemi.com
April 1988 Revised July 1999
74F125 Quad Buffer (3-STATE)
74F125 Quad Buffer (3-STATE)
Features
High impedance base inputs for reduced loading
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
IEEE/IEC
Connection Diagram
Unit Loading/Fan Out
Function Table
H = HIGH Voltage Level L = LOW Voltage Level Z = High Impedance X = Immaterial
Order Number Package Number Package Description
74F125SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 74F125SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F125PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Pin Names Description
U.L.
Input I
IH/IIL
HIGH/LOW
Output I
OH/IOL
An, B
n
Inputs 1.0/0.033 20 µA/20 µA
O
n
Outputs 600/106.6 (80) 12 mA/64 mA (48 mA)
Inputs Output
A
n
B
n
O
LLL LHH HXZ
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74F125
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
AC Electrical Characteristics
Storage Temperature 65°C to +150°C Ambient Temperature under Bias 55°C to +125°C Junction Temperature under Bias 55°C to +150°C V
CC
Pin Potential to Ground Pin 0.5V to +7.0V Input Voltage (Note 2) 0.5V to +7.0V Input Current (Note 2) 30 mA to +5.0 mA Voltage Applied to Output
in HIGH State (with V
CC
= 0V)
Standard Output 0.5V to V
CC
3-STATE Output 0.5V to +5.5V
Current Applied to Output
in LOW State (Max) twice the rated I
OL
(mA)
Free Air Ambient Temperature 0°C to +70°C Supply Voltage +4.5V to +5.5V
Symbol Parameter Min Typ Max Units
V
CC
Conditions
V
IH
Input HIGH Voltage 2.0 V Recognized as a HIGH Signal
V
IL
Input LOW Voltage 0.8 V Recognized as a LOW Signal
V
CD
Input Clamp Diode Voltage −1.2 V Min IIN = 18 mA
V
OH
Output HIGH 10% V
CC
2.4 IOH = 3 mA
Voltage 10% V
CC
2.0 VMin
IOH = 12 mA
5% V
CC
2.7 IOH = 3 mA
5% V
CC
2.0 IOH = 15 mA
V
OL
Output LOW 10% V
CC
0.55 V Min IOL = 64 mA
Voltage
I
IH
Input HIGH Current 20 µAMaxVIN = 2.7V
I
BVI
Input HIGH Current
100 µA0.0VVIN = 7.0V
Breakdown Test
I
IL
Input LOW Current 20.0 µAMaxVIN = 0.5V
I
OZH
Output Leakage Current 50 µAMaxV
OUT
= 2.7V
I
OZL
Output Leakage Current −50 µAMaxV
OUT
= 0.5V
I
OS
Output Short-Circuit Current −100 −225 mA Max V
OUT
= 0V
I
CEX
Output HIGH Leakage Current 250 µAMaxV
OUT
= V
CC
I
ZZ
Buss Drainage Test 500 µA0.0VV
OUT
= 5.25V
I
CCH
Power Supply Current 18.5 24.0 mA Max VO = HIGH
I
CCL
Power Supply Current 31.7 40.0 mA Max VO = LOW
I
CCZ
Power Supply Current 27.6 35.0 mA Max VO = HIGH Z
Symbol Parameter
TA = +25°CT
A
= 0°C to +70°C
Units
VCC = +5.0V VCC = +5.0V
CL = 50 pF CL = 50 pF
Min Typ Max Min Max
t
PLH
Propagation Delay 2.0 4.0 6.0 2.0 6.5
ns
t
PHL
3.0 4.6 7.5 3.0 8.0
t
PZH
Output Enable Time 3.5 4.7 7.5 3.0 8.5
ns
t
PZL
3.5 5.3 8.0 3.5 9.0
t
PHZ
Output Disable Time 1.5 3.9 5.5 1.5 6.0
ns
t
PLZ
1.5 4.0 6.0 1.5 6.5
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74F125
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
Package Number M14A
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
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74F125 Quad Buffer (3-STATE)
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N14A
Fairchild does no t assume any responsibility for use of an y circuitry d escribed, no c ircuit patent l icenses are impl ied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea­sonably expected to result in a sig nificant injury to the user.
2. A critical com ponen t in any com pone nt of a life s upport device or system w hose fa ilure to perform can be r ea­sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
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