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查询74F125供应商
74F125
Quad Buffer (3-STATE)
Features
■ High impedance base inputs for reduced loading
Ordering Code:
Order Number Package Number Package Description
74F125SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
74F125SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F125PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
74F125 Quad Buffer (3-STATE)
April 1988
Revised July 1999
Logic Symbol
IEEE/IEC
Unit Loading/Fan Out
Pin Names Description
An, B
n
O
n
Function Table
H = HIGH Voltage Level
L = LOW Voltage Level
Z = High Impedance
X = Immaterial
Connection Diagram
O
Input I
Output I
IH/IIL
OH/IOL
U.L.
HIGH/LOW
Inputs 1.0/0.033 20 µA/−20 µA
Outputs 600/106.6 (80) −12 mA/64 mA (48 mA)
Inputs Output
A
n
LLL
LHH
HXZ
B
n
© 1999 Fairchild Semiconductor Corporation DS009475 www.fairchildsemi.com
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Absolute Maximum Ratings(Note 1) Recommended Operating
Storage Temperature −65°C to +150°C
74F125
Ambient Temperature under Bias −55°C to +125°C
Junction Temperature under Bias −55°C to +150°C
V
Pin Potential to Ground Pin −0.5V to +7.0V
CC
Input Voltage (Note 2) −0.5V to +7.0V
Input Current (Note 2) −30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with V
CC
= 0V)
Standard Output −0.5V to V
3-STATE Output −0.5V to +5.5V
Current Applied to Output
in LOW State (Max) twice the rated I
OL
Conditions
Free Air Ambient Temperature 0°C to +70°C
Supply Voltage +4.5V to +5.5V
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
CC
under these conditions is not implied.
Note 2: Either v oltage limit or current limit is sufficient to protect inputs.
(mA)
DC Electrical Characteristics
Symbol Parameter Min Typ Max Units
V
V
V
V
V
I
I
I
I
I
I
I
I
I
I
I
IH
IL
CD
OH
OL
IH
BVI
IL
OZH
OZL
OS
CEX
ZZ
CCH
CCL
CCZ
Input HIGH Voltage 2.0 V Recognized as a HIGH Signal
Input LOW Voltage 0.8 V Recognized as a LOW Signal
Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA
Output HIGH 10% V
Voltage 10% V
5% V
5% V
Output LOW 10% V
Voltage
2.4 IOH = −3 mA
CC
2.0
CC
2.7 IOH = −3 mA
CC
2.0 IOH = −15 mA
CC
CC
0.55 V Min IOL = 64 mA
Input HIGH Current 20 µAMaxVIN = 2.7V
Input HIGH Current
Breakdown Test
100 µA0.0VVIN = 7.0V
Input LOW Current −20.0 µAMaxVIN = 0.5V
Output Leakage Current 50 µAMaxV
Output Leakage Current −50 µAMaxV
Output Short-Circuit Current −100 −225 mA Max V
Output HIGH Leakage Current 250 µAMaxV
Buss Drainage Test 500 µA0.0VV
Power Supply Current 18.5 24.0 mA Max VO = HIGH
Power Supply Current 31.7 40.0 mA Max VO = LOW
Power Supply Current 27.6 35.0 mA Max VO = HIGH Z
AC Electrical Characteristics
TA = +25°CT
Symbol Parameter
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Propagation Delay 2.0 4.0 6.0 2.0 6.5
Output Enable Time 3.5 4.7 7.5 3.0 8.5
Output Disable Time 1.5 3.9 5.5 1.5 6.0
VCC = +5.0V VCC = +5.0V
CL = 50 pF CL = 50 pF
Min Typ Max Min Max
3.0 4.6 7.5 3.0 8.0
3.5 5.3 8.0 3.5 9.0
1.5 4.0 6.0 1.5 6.5
V
CC
VMin
IOH = −12 mA
= 0°C to +70°C
A
OUT
OUT
OUT
OUT
OUT
Conditions
= 2.7V
= 0.5V
= 0V
= V
CC
= 5.25V
Units
ns
ns
ns
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Physical Dimensions inches (millimeters) unless otherwise noted
74F125
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14A
Package Number M14D
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
74F125 Quad Buffer (3-STATE)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Fairchild does no t assume any responsibility for use of an y circuitry d escribed, no c ircuit patent l icenses are i mplied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a sig nificant injury to the
user.
Package Number N14A
2. A critical com ponen t in any com pone nt of a life s uppor t
device or system w hose fa ilure to perform can be r easonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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