Datasheet 74F114SC, 74F114PC, 74F114SCX Datasheet (Fairchild Semiconductor)

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April 1988 Revised August 1999

74F114 Dual JK Negative Edge-Triggered Flip-Flop

with Common Clocks and Clears

General Description

The 74F114 contains two high-speed JK flip-flops with common Clock and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the tr ansition time. The J and K i nputs can change when the clock is in either state wi thout affecting the flip-flop, provided tha t they are in the desired sta te during the recommen ded setup and hold time s relative to the falling edge of the clock. A LOW signal on S

or C

prevents clocking and forces Q or Q HIGH, respe ctively.

Simultane o us LOW signals on S

and CD force both Q and

HIGH.

Asynchronous Inputs:

LOW input to S

sets Q to HIGH level

LOW input to C

sets Q to LOW level

Clear and Set are independent of Clock Simultaneous LOW on C

and S

makes both Q and Q HIGH

Ordering Code:

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Logic Symbols

IEEE/IEC

Connection Diagram

Order Number Package Number Package Description

74F114SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 74F114PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

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74F114

Unit Loading/Fan Out

Truth Table

H (h) = HIGH Voltage Level L (h) = LOW Voltage Level X = Immaterial



= HIGH-to-LOW C loc k Transit ion

(Q0) = Before HIGH-to-LOW Transition of Clock

Lower case letters indicate the state of the ref erenced input or output one setup time prior to the H I GH-to-LOW clock tra ns it ion.

Logic Diagram

(one half shown)

Please note that this diagram is provided o nly f or t he understanding of lo gic operations and should not be used to estimate propagation delays.

Pin Names Description

U.L. Input I

IH/IIL

HIGH/LOW Output IOH/I

J1, J2, K1, K2Data Inputs 1.0/1.0 20 µA/−0.6 mA CP

Clock Pulse Input (Active Falling Edge) 1.0/8.0 20 µA/−4.8 mA

Direct Clear Input (Active LOW) 1.0/10.0 20 µA/−6.0 mA

, S

Direct Set Inputs (Active LOW) 1.0/5.0 20 µA/−3.0 mA

, Q2, Q1, Q2Outputs 50/33.3 −1 mA/20 mA

Inputs Outputs

CDCP JKQQ

LHXXXHL HLXXXLH LLXXXHH HH



hhQ0Q



lhLH



hlHL



llQ0Q

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74F114

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: Absolute maximum ratings are values beyon d which the device

may be damaged or have its useful life impaired . Functional operation under these condit ions is not implied.

Note 2: Either voltage limit or curren t limit is sufficient to protect in puts.

DC Electrical Characteristics

Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C V

Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output

in HIGH State (with V

= 0V)

Standard Output −0.5V to V

3-STATE Output −0.5V to +5.5V

Current Applied to Output

in LOW State (Max) twice the rated I

(mA)

Free Air Ambi ent Temperature 0°C to +70°C Supply Voltage +4.5V to +5.5V

Symbol Parameter Min Typ Max Units

Conditions

Input HIGH Voltage 2.0 V Recognized as a HIGH Signal

Input LOW Voltage 0.8 V Recognized as a LOW Signal

Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA

Output HIGH 10% V

2.5 V Min IOH = −1 mA

Voltage 5% V

2.7 IOH = −1 mA

Output LOW 10% V

0.5 V Min IOL = 20 mA

Voltage

Input HIGH

5.0 µAMaxVIN = 2.7V

Current

BVI

Input HIGH Current

7.0 µAMaxVIN = 7.0V

Breakdown Test

CEX

Output High

50 µAMaxV

OUT

= V

Leakage Current

Input Leakage

4.75 V 0.0

IID = 1.9 µA

Test All Other Pins Grounded

Output Leakage

3.75 µA0.0

IOD

= 150 mV

Circuit Current All Other Pins Grounded

Input LOW Current −0.6

mA Max

VIN = 0.5V (Jn, Kn)

−3.0

VIN = 0.5V (SDn)

−4.8

VIN = 0.5V (CP)

−6.0

VIN = 0.5V (CDn)

Output Short-Circuit Current −60 −150 mA Max V

OUT

= 0V

CCH

Power Supply Current 12.0 19.0 mA Max VO = HIGH

CCL

Power Supply Current 12.0 19.0 mA Max VO = LOW

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74F114

AC Electrical Characteristics

AC Operating Requirements

Symbol Parameter

TA = +25°CT

= 0°C to +70°C

Units

VCC = +5.0V VCC = +5.0V

CL = 50 pF CL = 50 pF

Min Typ Max Min Max

MAX

Maximum Clock Frequency 75 95 70 MHz

PLH

Propagation Delay 3.0 5.0 6.5 3.0 7.5

PHL

CP to Qn or Q

3.0 5.5 7.5 3.0 8.5

PLH

Propagation Delay 3.0 4.5 6.5 3.0 7.5

PHL

CDn or SDn to Qn or Q

3.0 4.5 6.5 3.0 7.5

Symbol Parameter

TA = +25°CT

= 0°C to +70°C

UnitsVCC = +5.0V VCC = +5.0V

Min Max Min Max

tS(H) Setup Time, HIGH or LOW 4.0 5.0

tS(L)

Jn or Kn to CP

3.0 3.5 tH(H) Hold Time, HIGH or LOW 0 0 tH(L)

Jn or Kn to CP

tW(H)

CP Pulse Width

4.5 5.0

tW(L) HIGH or LOW 4.5 5.0 tW(L)

CDn or SDn Pulse Width,

4.5 5.0 ns

LOW

REC

Recovery Time 4.0 5.0 ns SDn, CDn, to CP

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74F114

Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow

Package Number M14A

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74F114 Dual JK Negative Edge-Triggered Flip-Flop

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N14A

Fairchild does not assume any responsibility for use of any circuitry described, no circuit pate nt licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or syste ms which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant inju ry to the user.

2. A critical component i n any compon ent of a lif e support device or system whose failu re to perform can be reasonably expected to ca use the fa i lure of the life su pp ort device or system, or to affect its safety or effectiveness.

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