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74F114
Dual JK Negative Edge-Triggered Flip-Flop
with Common Clocks and Clears
74F114 Dual JK Negative Edge-Triggered Flip-Flop
April 1988
Revised August 1999
General Description
The 74F114 contains two high-speed JK flip-flops with
common Clock and Clear inputs. Synchronous state
changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not
directly related to th e transition time. The J and K i nputs
can change when the clock is in either state wi thout affecting the flip-flop, provided tha t they are in the desired sta te
during the recommen ded setup and hold time s relative to
the falling edge of the clock. A LOW signal on S
prevents clocking and forces Q or Q HIGH, respectively.
or C
D
Simultane o us LO W signals on S
HIGH.
Q
Asynchronous Inputs:
LOW input to S
LOW input to C
Clear and Set are independent of Clock
Simultaneous LOW on C
D
makes both Q and Q HIGH
sets Q to HIGH level
D
sets Q to LOW level
D
and CD force both Q and
D
and S
D
D
Ordering Code:
Order Number Package Number Package Description
74F114SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
74F114PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering cod e.
Logic Symbols
IEEE/IEC
Connection Diagram
© 1999 Fairchild Semiconductor Corporation DS009474 www.fairchildsemi.com
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Unit Loading/Fan Out
74F114
Pin Names Description
U.L. Input I
HIGH/LOW Output IOH/I
J1, J2, K1, K2Data Inputs 1.0/1.0 20 µA/−0.6 mA
CP
C
D
, S
S
D1
D2
, Q2, Q1, Q2Outputs 50/33.3 −1 mA/20 mA
Q
1
Clock Pulse Input (Active Falling Edge) 1.0/8.0 20 µA/−4.8 mA
Direct Clear Input (Active LOW) 1.0/10.0 20 µA/−6.0 mA
Direct Set Inputs (Active LOW) 1.0/5.0 20 µA/−3.0 mA
Truth Table
Inputs Outputs
CDCP JKQQ
S
D
LHXXXHL
HLXXXLH
LLXXXHH
HH
HH
HH
HH
H (h) = HIGH Voltage Level
L (h) = LOW Voltage Level
X = Immaterial
= HIGH-to-LOW C loc k Transit ion
Q
(Q0) = Before HIGH-to-LOW Transition of Clock
0
Lower case letters indicate the state of the ref erenced input or outp ut one setup time prior to the HI GH-to-LOW clock tra ns it io n.
hhQ0Q
lhLH
hlHL
llQ0Q
0
0
IH/IIL
OL
Logic Diagram
(one half shown)
Please note that this diagram is provided o nly f or t he understanding of lo gic operations and shou ld not be used to estimate propagation delays.
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Absolute Maximum Ratings(Note 1) Recommended Operating
Storage Temperature −65°C to +150°C
Ambient Temperature under Bias −55°C to +125°C
Junction Temperature under Bias −55°C to +150°C
Pin Potential to Ground Pin −0.5V to +7.0V
V
CC
Input Voltage (Note 2) −0.5V to +7.0V
Input Current (Note 2) −30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with V
CC
= 0V)
Standard Output −0.5V to V
3-STATE Output −0.5V to +5.5V
Current Applied to Output
in LOW State (Max) twice the rated I
OL
Conditions
Free Air Ambient Temperature 0°C to +70°C
Supply Voltage +4.5V to +5.5V
Note 1: Absolute maximum ratings are values beyon d which the device
may be damaged or have its useful life impaired . Functional operation
CC
under these condit ions is not implied.
Note 2: Either voltage limit or curren t limit is sufficient to protect in puts.
(mA)
DC Electrical Characteristics
74F114
Symbol Parameter Min Typ Max Units
V
V
V
V
V
I
IH
I
BVI
I
CEX
V
I
OD
I
IL
I
OS
I
CCH
I
CCL
IH
IL
CD
OH
OL
ID
Input HIGH Voltage 2.0 V Recognized as a HIGH Signal
Input LOW Voltage 0.8 V Recognized as a LOW Signal
Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA
Output HIGH 10% V
Voltage 5% V
Output LOW 10% V
Voltage
Input HIGH
Current
Input HIGH Current
Breakdown Te st
Output High
Leakage Current
Input Leakage
Test All Other Pins Grounded
Output Leakage
Circuit Current All Other Pins Grounded
Input LOW Current −0.6
Output Short-Circuit Current −60 −150 mA Max V
Power Supply Current 12.0 19.0 mA Max VO = HIGH
Power Supply Current 12.0 19.0 mA Max VO = LOW
2.5 V Min IOH = −1 mA
CC
2.7 IOH = −1 mA
CC
CC
4.75 V 0.0
0.5 V Min IOL = 20 mA
5.0 µAMaxVIN = 2.7V
7.0 µAMaxVIN = 7.0V
50 µAMaxV
3.75 µA0.0
−3.0
−4.8
−6.0
V
mA Max
CC
IID = 1.9 µA
V
VIN = 0.5V (Jn, Kn)
VIN = 0.5V (SDn)
VIN = 0.5V (CP)
VIN = 0.5V (CDn)
= V
OUT
= 150 mV
IOD
= 0V
OUT
Conditions
CC
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AC Electrical Characteristics
74F114
Symbol Parameter
f
t
t
t
t
MAX
PLH
PHL
PLH
PHL
Maximum Clock Frequency 75 95 70 MHz
Propagation Delay 3.0 5.0 6 .5 3.0 7.5
CP to Qn or Q
Propagation Delay 3.0 4.5 6 .5 3.0 7.5
CDn or SDn to Qn or Q
n
n
TA = +25°CT
VCC = +5.0V VCC = +5.0V
CL = 50 pF CL = 50 pF
Min Typ Max Min Max
3.0 5.5 7.5 3.0 8.5
3.0 4.5 6.5 3.0 7.5
AC Operating Requirements
TA = +25°CT
Symbol Parameter
tS(H) Setup Time, HIGH or LOW 4.0 5.0
tS(L)
tH(H) Hold Time, HIGH or LOW 0 0
tH(L)
tW(H)
tW(L) HIGH or LOW 4.5 5.0
tW(L)
t
REC
Jn or Kn to CP
Jn or Kn to CP
CP Pulse Width
CDn or SDn Pulse Width,
LOW
Recovery Time 4.0 5.0 ns
SDn, CDn, to CP
Min Max Min Max
3.0 3.5
00
4.5 5.0
4.5 5.0 ns
= 0°C to +70°C
A
= 0°C to +70°C
A
Units
ns
ns
UnitsVCC = +5.0V VCC = +5.0V
ns
ns
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Physical Dimensions inches (millimeters) unless otherwise noted
74F114
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
Package Number M14A
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
74F114 Dual JK Negative Edge-Triggered Flip-Flop
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Fairchild does not assume any responsibility for us e of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significan t injury to the
user.
Package Number N14A
2. A critical component in any compon ent of a lif e supp ort
device or system whose failu re to perform can be reasonably expected to ca use the fa i lure of the li fe su pp ort
device or system, or to affect its safety or effectiveness.
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