Datasheet 74F113SJX, 74F113SJ, 74F113SCX, 74F113SC, 74F113PC Datasheet (Fairchild Semiconductor)

© 1999 Fairchild Semiconductor Corporation DS009473 www.fairchildsemi.com

April 1988
Revised July 1999

74F113 Dual JK Negative Edge-Triggered Flip-Flop

74F113
Dual JK Negative Edge-Triggered Flip-Flop

General Description

The 74F113 offers individual J, K, Set and Cl ock inputs.
When the clock goes HIGH the inputs are enabled and
data may be entered. The logic level of the J and K inputs
may be changed when the clock pulse is HIGH and the flip­flop will perf orm according to the Truth Table as long as
minimum setup and h old tim es are obs erved . Inp ut dat a is

transferred t o the outputs on the falling edge of the clock
pulse.

Asynchronous input:

LOW input to S

D

sets Q to HIGH level

Set is independent of clock

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

IEEE/IEC

Connection Diagram

Order Number Package Number Package Description

74F113SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
74F113SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F113PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

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74F113

Unit Loading/Fan Out

Tr uth Table

H (h) = HIGH Voltage Level
L (l) = LOW Voltage l evel
]



= HIGH-to-LOW Clock Transition
X = Immaterial
Q

0 (Q0

) = Before HIGH-to-LOW Transition of Clock

Lower case letters indicate the state of the referenced i nput or output prior to the HIGH-to-LOW clock transition.

Logic Diagram

(One Half Shown)

Please note that this diagram is provided only for the understanding of logic operations and should not be use d to estimate propagation delays.

Pin Names Description

U.L.

Input I

IH/IIL

HIGH/LOW

Output I

OH/IOL

J1, J2, K1, K2Data Inputs 1.0/1.0 20 µA/−0.6 mA
CP

1

, CP

2

Clock Pulse Inputs (Active Falling Edge) 1.0/4.0 20 µA/−2.4 mA

S

D1

, S

D2

Direct Set Inputs (Active LOW) 1.0/5.0 20 µA/−3.0 mA

Q

1

, Q2, Q1, Q2Outputs 50/33.3 −1 mA/20 mA

Inputs Outputs

S

D

CP JK Q Q

LXXXHL
H



hhQ0Q

0

H



lhL H

H



hl H L

H



llQ0Q

0

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74F113

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: Absolute maximum ratings are values beyond which the device

may be damaged or have its useful life impaired. Functional operation
under these conditio ns is not implied.

Note 2: Either voltage limit or curre nt limit is sufficie nt to prote ct input s.

DC Electr ic al C h ar acteristi cs

Storage Temperature −65°C to +150°C
Ambient Temperature under Bias −55°C to +125°C
Junction Temperature under Bias −55°C to +150°C
V

CC

Pin Potential to Ground Pin −0.5V to +7.0V
Input Voltage (Note 2) −0.5V to +7.0V
Input Current (Note 2) −30 mA to +5.0 mA
Voltage Applied to Output

in HIGH State (with V

CC

= 0V)

Standard Output −0.5V to V

CC

3-STATE Ou tput −0.5V to +5.5V

Current Applied to Output

in LOW State (Max) twice the rated I

OL

(mA)

Free Air Ambient Temperature 0°C to +70°C
Supply Voltage +4.5V to +5.5V

Symbol Parameter Min Typ Max Units

V

CC

Conditions

V

IH

Input HIGH Voltage 2.0 V Recognized as a HIGH Signal

V

IL

Input LOW Voltage 0.8 V Recognized as a LOW Signal

V

CD

Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA

V

OH

Output HIGH 10% V

CC

2.5 V Min IOH = −1 mA

Voltage 5% V

CC

2.7 IOH = −1 mA

V

OL

Output LOW 10% V

CC

0.5 V Min IOL = 20 mA

Voltage

I

IH

Input HIGH

5.0 µAMaxVIN = 2.7V

Current

I

BVI

Input HIGH Current

7.0 µAMaxVIN = 7.0V

Breakdown Test

I

CEX

Output HIGH

50 µAMax

V

OUT

= V

CC

Leakage Current

V

ID

Input Leakage

4.75 V 0.0

IID = 1.9 µA

Test All Other Pins Grounded

I

OD

Output Leakage

3.75 µA0.0

V

IOD

= 150 mV

Circuit Current All Other Pins Grounded

I

IL

Input LOW Current −0.6 VIN = 0.5V (Jn, Kn)

−2.4 mA Max VIN = 0.5V (CPn)

−3.0 VIN = 0.5V (SDn)

I

OZH

Output Leakage Current 50 µAMaxV

OUT

= 2.7V

I

OZL

Output Leakage Current −50 µAMaxV

OUT

= 0.5V

I

OS

Output Short-Circuit Current −60 −150 mA Max V

OUT

= 0V

I

CC

Power Supply Current 12 19 mA Max

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74F113

AC Electrical Characteristics

AC Operating Requirements

Symbol Parameter

TA = +25°CT

A

= 0°C to +70°C

Units

VCC = +5.0V VCC = +5.0V

CL = 50 pF CL = 50 pF

Min Typ Max Min Max

f

MAX

Maximum Clock Frequency 85 105 80 MHz

t

PLH

Propagation Delay 2.0 4.0 6.0 2.0 7.0

ns

t

PHL

CPn to Qn or Q

n

2.0 4.0 6.0 2.0 7.0

t

PLH

Propagation Delay 2.0 4.5 6.5 2.0 7.5

ns

t

PHL

SDn to Qn or Q

n

2.0 4.5 6.5 2.0 7.5

Symbol Parameter

TA = +25°CT

A

= 0°C to +70°C

UnitsVCC = +5.0V VCC = +5.0V

Min Max Min Max

tS(H) Setup Time, HIGH or LOW 4.0 5.0

ns

tS(L)

Jn or Kn to CP

n

3.0 3.5
tH(H) Hold Time, HIGH or LOW 0 0
tH(L)

Jn or Kn to CP

n

00

tW(H)

CPn Pulse Width

4.5 5.0

ns

tW(L) HIGH or LOW 4.5 5.0
tW(L)

SDn Pulse Width, LOW

4.5 5.0 ns
t

REC S

Dn

to CP

n

4.0 5.0 ns

Recovery Time

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74F113

Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow

Package Number M14A

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M14D

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74F11 3 Dual JK Negative Edge-T riggered Flip-Flop

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N14A

Fairchild does no t assume any responsibility for use of an y circuitry d escribed, no c ircuit patent l icenses are impl ied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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SEMICONDUCTOR CORPORATION. As used herein:

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which, (a) are intended for surgical implant into the
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to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea­sonably expected to result in a sig nificant injury to the
user.

2. A critical com ponen t in any com pone nt of a life s upport
device or system w hose fa ilure to perform can be r ea­sonably expected to cause the failure of the life support
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