Datasheet 74F112SJX, 74F112SJ, 74F112SCX, 74F112SC, 74F112PC Datasheet (Fairchild Semiconductor)

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April 1988 Revised July 1999

74F112 Dual JK Negative Edge-Triggered Flip-Flop

General Description

The 74F112 contains two indepen dent, high -spee d JK flipflops with Direct S et and Clear inputs. Sy nchronous state changes are in itiated by the fa lling edg e o f the c lock . Triggering occurs at a voltage level of th e clock and is not directly related to t he transition time. The J and K i nputs can change when the clock is in either state w ithout affecting the flip-flop, provided that the y are in the desired st ate during the recommen ded setup and hold ti mes relative to the falling edge of the clock. A LOW signal on S

or C

prevents clocki ng and forces Q or Q HIGH, respectivel y.

Simultaneous LOW signals on S

and CD force both Q and

HIGH.

Asynchronous Inputs:

LOW input to S

sets Q to HIGH level

LOW input to C

sets Q to LOW level

Clear and Set are independent of clock Simultaneous LOW on C

and SD makes both Q

and Q

HIGH

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

IEEE/IEC

Connection Diagram

Order Number Package Number Package Description

74F112SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74F112SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F112PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

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74F112

Unit Loading/Fan Out

Tr uth Table

H (h) = HIGH Voltage Level L (l) = LOW Voltage Level X = Immaterial



= HIGH-to-LOW Clock Transition

0(Q0

) = Before HIGH-to-LOW Transition of C lock

Lower case letters indicate the state of the referenced input or output one setup time prior to the HIGH-to-LOW clock transition.

Logic Diagram

(One Half Shown)

Please note that this diagram is provided only for the understanding of logic operations and should not be use d to estimate propagation delays.

Pin Names Description

U.L.

Input I

IH/IIL

HIGH/LOW

Output I

OH/IOL

J1, J2, K1, K2Data Inputs 1.0/1.0 20 µA/−0.6 mA CP

, CP

Clock Pulse Inputs (Active Falling Edge) 1.0/4.0 20 µA/−2.4 mA

, C

Direct Clear Inputs (Active LOW) 1.0/5.0 20 µA/−3.0 mA

, S

Direct Set Inputs (Active LOW) 1.0/5.0 20 µA/−3.0 mA

, Q2, Q1, Q2Outputs 50/33.3 −1 mA/20 mA

Inputs Outputs

CP JKQ Q

LHXXXHL HLXXXLH LLXXXHH HH



hhQ0Q



lhL H



hlH L



llQ0Q

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74F112

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: Absolute maximum ratings are values beyond which the device

may be damaged or have its useful life impaired. Functional operation under these conditio ns is not implied.

Note 2: Either voltage limit or curre nt limit is sufficie nt to prote ct input s.

DC Electr ic al C h ar acteristi cs

Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C V

Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output

in HIGH State (with V

= 0V)

Standard Output −0.5V to V

3-STATE Output −0.5V to +5.5V

Current Applied to Output

in LOW State (Max) twice the rated I

(mA)

Free Air Ambient Temperature 0°C to +70°C Supply Voltage +4.5V to +5.5V

Symbol Parameter M in Typ Max Units

Conditions

Input HIGH Voltage 2.0 V Recognized as a HIGH Signal

Input LOW Voltage 0.8 V Recognized as a LOW Signal

Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA

Output HIGH 10% V

2.5 V Min IOH = −1 mA

Voltage 5% V

2.7 IOH = −1 mA

Output LOW 10% V

0.5 V Min IOL = 20 mA

Voltage

Input HIGH

5.0 µAMaxVIN = 2.7V

Current

BVI

Input HIGH Current

7.0 µAMaxVIN = 7.0V

Breakdown Test

CEX

Output HIGH

50 µAMaxV

OUT

= V

Leakage Current

Input Leakage

4.75 V 0.0

IID = 1.9 µA

Test All other pins grounded

Output Leakage

3.75 µA0.0

IOD

= 150 mV

Circuit Current All other pins grounded

Input LOW Current −0.6 VIN = 0.5V (Jn, Kn)

−2.4 mA Max

VIN = 0.5V (CPn)

−3.0

VIN = 0.5V (CDn, SDn)

Output Short-Circuit Current −60 −150 mA Max V

OUT

= 0V

CCH

Power Supply Current 12 19 mA Max VO = HIGH

CCL

Power Supply Current 12 19 mA Max VO = LOW

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74F112

AC Electrical Characteristics

AC Operating Requirements

Symbol Parameter

TA = +25°CT

= 0°C to +70°C

Units

VCC = +5.0V VCC = +5.0V

CL = 50 pF CL = 50 pF

Min Typ Max Min Max

MAX

Maximum Clock Frequency 85 105 80 MHz

PLH

Propagation Delay 2.0 5.0 6.5 2.0 7.5

PHL

CPn to Qn or Q

2.0 5.0 6.5 2.0 7.5

PLH

Propagation Delay 2.0 4.5 6.5 2.0 7.5

PHL

CDn, SDn to Qn, Q

2.0 4.5 6.5 2.0 7.5

Symbol Parameter

TA = +25°CT

= 0°C to +70°C

UnitsVCC = +5.0V VCC = +5.0V

Min Max Min Max

tS(H) Setup Time, HIGH or LOW 4.0 5.0

tS(L)

Jn or Kn to CP

3.0 3.5 tH(H) Hold Time, HIGH or LOW 0 0 tH(L)

Jn or Kn to CP

tW(H)

CP Pulse Width

4.5 5.0

tW(L) HIGH or LOW 4.5 5.0 tW(L) Pulse Width, LOW

4.5 5.0 ns

CDn or S

REC

Recovery Time

4.0 5.0 ns

SDn, CDn to CP

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74F112

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

Package Number M16A

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M16D

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74F11 2 Dual JK Negative Edge-T riggered Flip-Flop

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N16E

Fairchild does no t assume any responsibility for use of an y circuitry d escribed, no c ircuit patent l icenses are impl ied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a sig nificant injury to the user.

2. A critical com ponen t in any com pone nt of a life s upport device or system w hose fa ilure to perform can be r easonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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