Datasheet 74F112 Datasheet (Fairchild)

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74F112 Dual JK Negative Edge-Triggered Flip-Flop

April 1988 Revised July 1999

General Description

The 74F112 contains two indepen dent, high -spee d JK flipflops with Direct S et and Clear inputs. Sy nchronous state changes are in iti ated by th e fa ll ing edg e o f the cloc k. Triggering occurs at a voltage level of the clock and is not directly related to t he transition time. The J an d K inputs can change when the clock is in either stat e without affecting the flip-flop, provided that the y are in the desired st ate during the recommen ded setup and ho ld times relative to the falling edge of the clock. A LOW signal on S prevents clocki ng and forces Q or Q HIGH, respectivel y.

or C

Simultaneous LOW signals on S

HIGH.

Q Asynchronous Inputs:

LOW input to S LOW input to C Clear and Set are independent of clock

Simultaneous LOW on C

and Q

sets Q to HIGH level

sets Q to LOW level

HIGH

and CD force both Q and

and SD makes both Q

Ordering Code:

Order Number Package Number Package Description

74F112SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74F112SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F112PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel . Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC

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Unit Loading/Fan Out

74F112

Pin Names Description

U.L.

HIGH/LOW

J1, J2, K1, K2Data Inputs 1.0/1.0 20 µA/−0.6 mA CP

, CP

, C

, S

, Q2, Q1, Q2Outputs 50/33.3 −1 mA/20 mA

Clock Pulse Inputs (Active Falling Edge) 1.0/4.0 20 µA/−2.4 mA

Direct Clear Inputs (Active LOW) 1.0/5.0 20 µA/−3.0 mA

Direct Set Inputs (Active LOW) 1.0/5.0 20 µA/−3.0 mA

Tr uth Table

Inputs Outputs

LHXXXHL HLXXXLH LLXXXHH HH HH HH HH

H (h) = HIGH Voltage Level L (l) = LOW Voltage Level X = Immaterial



= HIGH-to-LOW Clock Transition

) = Before HIGH-to-LOW Trans ition of Clock

0(Q0

Lower case letters indicate the state of the referenced input or output one setup time prior to the HIGH-to-LOW clock transition.

CP JKQ Q



hhQ0Q



lhL H



hlH L



llQ0Q

Input I

Output I

IH/IIL

OH/IOL

Logic Diagram

(One Half Shown)

Please not e that this diagram is provided only for the understanding of logic operations and should not be use d to estimate propagation delays.

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Absolute Maximum Ratings(Note 1) Recommended Operating

Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C V

Pin Potential to Ground Pin −0.5V to +7.0V

Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output

in HIGH State (with V

= 0V) Standard Output −0.5V to V 3-STATE Output −0.5V to +5.5V

Current Applied to Output

in LOW State (Max) twice the rated I

Conditions

Free Air Ambient Temperature 0°C to +70°C Supply Voltage +4.5V to +5.5V

Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation

under these conditio ns is not implied. Note 2: Either voltage limit or curr ent limit is suffic ient to prote ct input s.

(mA)

DC Electr ic al C h ar acteristi cs

74F112

Symbol Parameter Min Typ Max Units

V V V V

I I I

IH IL CD OH

BVI

CEX

OS CCH CCL

Input HIGH Voltage 2.0 V Recognized as a HIGH Signal Input LOW Voltage 0.8 V Recognized as a LOW Signal Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA Output HIGH 10% V Voltage 5% V Output LOW 10% V Voltage Input HIGH Current Input HIGH Current Breakdown Test Output HIGH Leakage Current Input Leakage Test All other pins grounded Output Leakage Circuit Current All other pins grounded Input LOW Current −0.6 VIN = 0.5V (Jn, Kn)

Output Short-Circuit Current −60 −150 mA Max V Power Supply Current 12 19 mA Max VO = HIGH Power Supply Current 12 19 mA Max VO = LOW

2.5 V Min IOH = −1 mA

2.7 IOH = −1 mA

CC CC

4.75 V 0.0

0.5 V Min IOL = 20 mA

5.0 µAMaxVIN = 2.7V

7.0 µAMaxVIN = 7.0V

50 µAMaxV

3.75 µA0.0

−2.4 mA Max

−3.0

IID = 1.9 µA

VIN = 0.5V (CPn) VIN = 0.5V (CDn, SDn)

= V

OUT

= 150 mV

IOD

= 0V

OUT

Conditions

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AC Electrical Characteristics

74F112

Symbol Parameter

f t t

t t

MAX PLH PHL PLH PHL

Maximum Clock Frequency 85 105 80 MHz Propagation Delay 2.0 5.0 6.5 2.0 7.5

CPn to Qn or Q

Propagation Delay 2.0 4.5 6.5 2.0 7.5 CDn, SDn to Qn, Q

TA = +25°CT

VCC = +5.0V VCC = +5.0V

CL = 50 pF CL = 50 pF

Min Typ Max Min Max

2.0 5.0 6.5 2.0 7.5

2.0 4.5 6.5 2.0 7.5

AC Operating Requirements

TA = +25°CT

Symbol Parameter

Min Max Min Max

tS(H) Setup Time, HIGH or LOW 4.0 5.0 tS(L)

Jn or Kn to CP

tH(H) Hold Time, HIGH or LOW 0 0 tH(L)

tW(H)

Jn or Kn to CP CP Pulse Width

tW(L) HIGH or LOW 4.5 5.0 tW(L) Pulse Width, LOW

CDn or S

REC

Recovery Time SDn, CDn to CP

3.0 3.5

4.5 5.0

4.5 5.0 ns

4.0 5.0 ns

= 0°C to +70°C

Units

UnitsVCC = +5.0V VCC = +5.0V

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Physical Dimensions inches (millimeters) unless otherwise noted

74F112

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M16A

Package Number M16D

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N16E

74F11 2 Dual JK Negative Edge-T riggered Flip-Flop

Fairchild does no t assume any responsibility for use of an y circuitry d escribed, no c ircuit patent l icenses are i mplied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a sig nificant injury to the user.

2. A critical com ponen t in any com pone nt of a life s uppor t device or system w hose fa ilure to perform can be r easonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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