Page 1
查询74F1071供应商
74F1071
18-Bit Undershoot/Overshoot Clamp
and ESD Protection Device
74F1071 18-Bit Undershoot/Overshoot Clamp
October 1994
Revised August 1999
General Description
The 74F1071 is an 18-bit undershoot/overshoot clamp
which is designed to limit bus vol tages and also to prot ect
more sensitive devices from electrical overstress due to
electrostatic discharge (ESD). The inputs of the device
aggressively clamp vo ltage excursions nominally at 0.5V
below and 7V above ground.
Features
■ 18-bit array structure in 20-pin package
■ FAST Bipolar voltage clamping action
■ Dual center pin grounds for min inductance
■ Robust design for ESD protection
■ Low input capacitance
■ Optimum voltage clamping for 5V CMOS/TTL
applications
Ordering Code:
Order Number Package Number Package Description
74F1071SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F1071MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74F1071MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering cod e.
Connection Diagram
Note: Simplified Comp onent Representatio n
FAST is a regist ered trademark of Fair c hild Semiconductor C orporation.
© 1999 Fairchild Semiconductor Corporation DS011685 www.fairchildsemi.com
Page 2
Absolute Maximum Ratings(Note 1) Recommended Operating
Storage Temperature −65°C to +150°C
Ambient Temperature under Bias −65°C to +125°C
74F1071
Junction Temperature under Bias −65°C to +150°C
Input Voltage (Note 2) −0.5V to +6V
Input Current (Note 2) −200 mA to +50 mA
ESD (Note 3)
Human Body Model
(MIL-STD-883D method 3015.7) ±10 kV
IEC 801-2 ±6 kV
Machine Model (EIAJIC-121-1981) ±2 kV
DC Latchup Source Current
(JEDEC Method 17) ±500 mA
Package Power Dissipation @+70°C
SOIC Package 800 mW
Conditions
Free Air Ambient Temperature 0°C to +70°C
Reverse Bias Voltage 0V to 5.25 V
Thermal Resistance (θJA in Free Air)
SOIC Package 100°C/W
SSOP Package 110°C/W
Note 1: Absolute maximum ratings are DC values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditi ons is not implied.
Note 2: Voltage ratings may be e xceeded if curren t ratings and juncti on
temperature and pow er consumption rati ngs are not exceeded.
Note 3: ESD Rating for Dire ct contact discharge usi ng ESD Simulation
Tester. Higher rating ma y be realized in the actual application.
DC Electrical Characteristics
DC
Symbol Parameter
I
IH
V
V
I
CT
C
Input HIGH Current 1.5 10 50
Reverse Voltage 6.6 6.9 7.2 5.9 7.7
Z
Forward Voltage −0.3 −0.6 −0.9 −0.3 −0.9
F
Adjacent Input Crosstalk 3 %
Input Capacitance 25
IN
(small signal @ 1 MHz) 13 V
TA = +25°CT
Min Typ Max Min Max
320 100 V
7.1 7.5 8.0 IZ = 50 mA; Untested Inputs @ GND
−0.5 −1.1 −1.5 −0.5 −1.5 IF = −200 mA; Untested Inputs @ 5V
= 0°C to +70°C
A
Units Conditions
VIN = 5.25V; Untested Input @ GND
µA
= 5.5V; Untested Input @ GND
IN
IZ = 1 mA; Untested Inputs @ GND
V
IF = −18 mA; Untested Inputs @ 5V
V
V
= 0 V
BIAS
BIAS
= 5 V
DC
DC
pF
www.fairchildsemi.com 2
Page 3
DC Electrical Characteristics
Typical Forward and Reverse V/I
Typical Reverse Conduction
Characteristics
74F1071
Characteristics
Typical Forward Conduction
Characteristics
ESD Network CZ RZ
Human Body Model 100 pF 1500Ω
IEC 801-2 150 pF 330Ω
Simulated ESD Voltage Clamping Test Circuit
3 www.fairchildsemi.com
Page 4
DC Electrical Characteristics (Continued)
74F1071
Unclamped + 1 KV ESD Voltage
Waveform (IEC801-2 Network)
Unclamped - 1 KV ESD Volt age
Waveform (IEC801-2 Network)
Clamped + 1 KV ESD Voltage
Waveform (IEC801-2 Network)
Clamped - 1 KV ESD Voltage
Waveform (IEC801-2 Network)
Typical Application
74F1071 ESD Protection of ASIC on User Port
www.fairchildsemi.com 4
Page 5
Physical Dimensions inches (millimeters) unless otherwise noted
74F1071
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20B
Package Number MSA20
5 www.fairchildsemi.com
Page 6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
74F1071 18-Bit Undershoot/Overshoot Clamp
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Fairchild does not assume any responsibility for us e of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significan t injury to the
user.
www.fairchildsemi.com 6
Package Number MTC20
2. A critical component in any compon ent of a lif e supp ort
device or system whose failu re to perform can be reasonably expected to ca use the fa i lure of the li fe su pp ort
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
Loading...