Page 1
SN74ALS235
64 × 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SDAS108A – OCTOBER 1986 – REVISED SEPTEMBER 1993
D
Asynchronous Operation
D
Organized as 64 Words by 5 Bits
D
Data Rates From 0 to 25 MHz
D
3-State Outputs
D
Package Options Include Plastic
Small-Outline Packages (DW), Plastic
J-Leaded Chip Carriers (FN), and Standard
Plastic 300-mil DIPs (N)
description
The SN74ALS235 is a 320-bit memory utilizing
DW OR N PACKAGE
(TOP VIEW)
OE
1
20
HF
2
19
IR
3
18
SI
4
17
D0
5
16
D1
6
15
D2
7
14
D3
8
13
9
10
12
11
D4
GND
V
CC
AF/AE
SO
OR
Q0
Q1
Q2
Q3
Q4
RST
advanced low-power Schottky IMPACT
technology. It features high speed with fast
SI
FN PACKAGE
(TOP VIEW)
HF
OE
IR
3 2 1 20 19
4
5
6
7
8
910111213
D4
RST
GND
CC
V
Q4
AF/AE
18
17
16
15
14
Q3
SO
OR
Q0
Q1
Q2
fall-through times and is organized as 64 words by
5 bits.
A first-in, first-out (FIFO) memory is a storage
device that allows data to be written into and read
from its array at independent data rates. The
SN74ALS235 is designed to process data at rates
from 0 to 25 MHz in a bit-parallel format, word by
word.
Data is written into memory on the rising edge of
the shift-in (SI) input. When SI goes low, the first
data word ripples through to the output (see
Figure 1). As the FIFO fills up, the data words
stack up in the order they were written. When the
D0
D1
D2
D3
FIFO is full, additional shift-in pulses have no
effect. Data is shifted out of memory on the falling edge of the shift-out (SO) input (see Figure 2). When the FIFO
is empty , additional SO pulses have no effect. The last data word remains at the outputs until a new word falls
through or reset (RST
) goes low.
Status of the SN74ALS235 FIFO memory is monitored by the output-ready (OR), input-ready (IR),
almost-full / almost-empty (AF/AE), and half-full (HF) flags. When OR is high, valid data is available at the
outputs. OR is low when SO is high and stays low when the FIFO is empty . IR is high when the inputs are ready
to receive more data. IR is low when SI is high and stays low when the FIFO is full. AF/AE is high when the FIFO
contains eight or less words (see Figure 5) or 56 or more words (see Figure 6). AF/AE is low when the FIFO
contains between nine and 55 words. HF is high when the FIFO contains 32 or more words and is low when
the FIFO contains 31 words or less (see Figure 7).
When the FIFO is empty, input data is shifted to the output automatically when SI goes low. If SO is held high
during this time, the OR flag pulses high indicating valid data at the outputs (see Figure 3).
When the FIFO is full, data can be shifted in automatically by holding SI high and taking SO low. One propagation
delay after SO goes low, IR will go high. If SI is still high when IR goes high, data at the inputs are automatically
shifted in. Since IR is normally low when the FIFO is full and SI is high, only a high-level pulse is seen on the
IR output.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
IMPACT is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1993, Texas Instruments Incorporated
1
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SN74ALS235
64 × 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SDAS108A – OCTOBER 1986 – REVISED SEPTEMBER 1993
description (continued)
The FIFO must be reset after power up with a low-level pulse on the master reset (RST) input. This sets IR high
and OR low signifying that the FIFO is empty. Resetting the FIFO sets the outputs to a low logic level (see
Figure 1). If SI is high when RST
SI goes low. If SI goes low before RST
outputs are noninverting with respect to the data inputs and are at high impedance when the output-enable (OE
input is high. OE
does not affect the status-flag outputs (see Figure 2).
The SN74ALS235 is characterized for operation from 0°C to 70°C.
goes high, the input data is shifted in and IR goes low and remains low until
goes high, the input data will not be shifted in and IR goes high. Data
)
logic symbol
†
This symbol is in accordance with ANSI/IEEE Standard 91-1984 and IEC Publication 617-12.
†
FIFO 64 × 5
4
SI
18
SO
11
RST
1
OE
5
D0 Q0
6
D1
7
D2
8
D3
9
D4
5 + /C1
G2
4 –
G3
CT = 0
R
EN 6
1D
CTR
3
(CT > 0) G4
CT ≤ 8/CT ≥ 56
CT ≥ 32
2
CT < 64
(CT < 64) G5
CT > 0
6
17
19
16
15
14
13
12
2
3
OR
AF/AE
HF
IR
Q1
Q2
Q3
Q4
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 3
functional block diagram
1
OE
5
D0
6
D1
7
D2
8
D3
9
D4
FIFO
Input
Stage
SN74ALS235
64 × 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SDAS108A – OCTOBER 1986 – REVISED SEPTEMBER 1993
16
Q0
15
Q1
65 × 5 Bit
Register
FIFO
Output
Stage
14
13
12
Q2
Q3
Q4
IR
SI
RST
3
4
11
Input-
Control
Logic
Register-
Control
Logic
Flag-
Control
Logic
OutputControl
Logic
18
17
19
SO
OR
AF/AE
2
HF
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SN74ALS235
64 × 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SDAS108A – OCTOBER 1986 – REVISED SEPTEMBER 1993
logic diagram (positive logic)
OE
D0
D1
Data Inputs
D2
D3
RST
SI
SO
Word 64 Word 63
Word 57 Word 56Word 55 Word 54
1
Word 33 Word 32Word 31 Word 30
2
3
4
5
6
7
Continued on Next Page
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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64 × 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
logic diagram (positive logic) (continued)
1
Word 7Word 8Word 9Word 10
2
SDAS108A – OCTOBER 1986 – REVISED SEPTEMBER 1993
Word 3 Word 2
Word 1
SN74ALS235
Q0
Data
Q1
Outputs
Q2
Q3
OR
3
4
5
6
7
timing diagram
RST
SI
D4–D0
W1 W9
SO
Q4–Q0
IR
OR
AF/AE
HF
AF/AE
IR
W2 W8 W31 W32 W55 W56 Don’t Care W1 W1 W63 W64 W1
Word 1
Word 2
Word 55
Word 56 Invalid
†
Word 1
‡
Word 2 Word3
HF
Shift In
W1
Clear
†
The last data word shifted out of the FIFO remains at the output until a new word falls through or a RST pulse clears the FIFO.
‡
While the output data is considered valid only when the OR flag is high, the stored data remains at the output. Any additional words written into
the FIFO will stack up behind the first word and will not appear at the output until SO is taken low.
Almost
Empty+1
Full
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Almost
Full
Empty FullHalf
5
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SN74ALS235
64 × 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SDAS108A – OCTOBER 1986 – REVISED SEPTEMBER 1993
RST
t
su
SI
t
h
D4–D0
t
su
Full
IR
OR
Q4–Q0
NOTE A: SO is low.
SO
OR
IR
Full
t
PLH
t
PHL
t
Empty
pd
Figure 1. Master Reset and Data-In Waveforms
t
PLH
t
d(SOL-QX)
t
t
PHL
PLH
t
pd
t
PHL
t
PLH
t
PLH
Q4–Q0
t
dis
OE
NOTE A: SI is low.
6
t
t
en
pd
Figure 2. Data-Out Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SN74ALS235
64 × 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SDAS108A – OCTOBER 1986 – REVISED SEPTEMBER 1993
D4–D0
t
su
SI
t
h
SO
OR
Q4–Q0
SO
D4–D0
t
PLH
Empty
Invalid
t
w
t
d(QV-ORH)
Figure 3. Data Fall-Through Waveforms
SI
IR
Full Full
t
PLH
t
w
Figure 4. Automatic Data-In Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SN74ALS235
64 × 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SDAS108A – OCTOBER 1986 – REVISED SEPTEMBER 1993
SO
t
PLH
AF/AE
SI
Figure 5. Almost-Empty Waveforms
SI
t
PLH
t
PHL
AF/AE
SO
SI
HF
SO
Figure 6. Almost-Full Waveforms
t
PLH
Figure 7. Half-Full Waveforms
t
PHL
t
PHL
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 9
IOHHigh-level output current
mA
IOLLow-level output current
mA
twPulse duration
ns
tsuSetup time before SI↑
ns
SN74ALS235
64 × 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SDAS108A – OCTOBER 1986 – REVISED SEPTEMBER 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
Input voltage, V
Voltage applied to a disabled 3-state output 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.
(see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
A
0°C to 70°. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
recommended operating conditions
MIN NOM MAX UNIT
V
CC
V
IH
V
IL
f
clock
t
h
T
A
Supply voltage 4.5 5 5.5 V
High-level input voltage 2 V
Low-level input voltage 0.8 V
p
p
Clock frequency SI or SO 0 25 MHz
p
Hold time, data after SI↑ 17 ns
Operating free-air temperature 0 70 °C
Q outputs – 2.6
Flags – 0.4
Q outputs 24
Flags 8
SI or SO High or low 15
RST Low 15
Data 0
RST High (inactive) 15
†
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SN74ALS235
Any Q
V
4.5 V
Any Q
V
V
V
V
Flags
V
V
64 × 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SDAS108A – OCTOBER 1986 – REVISED SEPTEMBER 1993
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
V
IK
V
OH
Flags VCC = 4.5 V, IOH = –0.4 mA 2.7 3.4
OL
I
OZH
I
OZL
I
I
I
IH
I
IL
‡
I
O
I
CC
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
VCC = 4.5 V, II = –18 mA –1.2 V
=
CC
= 4.5
CC
= 4.5
CC
VCC = 5.5 V, VO = 2.7 V 20 µA
VCC = 5.5 V, VO = 0.4 V –20 µA
VCC = 5.5 V, VI = 7 V 0.1 mA
VCC = 5.5 V, VI = 2.7 V 20 µA
VCC = 5.5 V, VI = 0.4 V –0.1 mA
VCC = 5.5 V, VO = 2.25 V –30 –112 mA
VCC = 5.5 V High 105 160
IOH = –1 mA
IOH = –2.6 mA 2.4 3.2
IOL = 12 mA 0.25 0.4
IOL = 24 mA 0.35 0.5
IOL = 4 mA 0.25 0.4
IOL = 8 mA 0.35 0.5
Low 112 165
Disabled 115 170
V
mA
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 11
f
MH
IR
ns
SI↓
AF/AE
ns
OR
ns
SO↓
AF/AE
ns
t
RST↓
ns
64 × 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SDAS108A – OCTOBER 1986 – REVISED SEPTEMBER 1993
switching characteristics (see Figure 9)
VCC = 5 V,
CL = 50 pF,
PARAMETER
max
‡
tw
§
tw
t
d(QV-ORH)
t
d(SOL-QX)
t
pd
t
PHL
t
PLH
¶
t
PLH
t
PHL
t
PLH
t
PLH
t
pd
t
PHL
t
PLH
¶
t
PLH
t
PHL
t
PLH
t
PHL
t
PHL
t
PLH
PHL
t
dis
t
en
†
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
‡
The IR output pulse occurs when the FIFO is full, SI is high, and SO is pulsed (see Figure 4).
§
The OR output pulse occurs when the FIFO is empty, SO is high, and SI is pulsed (see Figure 3).
¶
Data throughput or fall-through times
FROM
(INPUT)
SI 30 25
SO 30 25
IR high 15 8 ns
OR high 19 8 ns
Q valid before OR↑ 6 9 –5 12 ns
Q valid after SO↓ 13 4 ns
SI↓ Q 600 800 350 1000 ns
SI↑
SI↓
SI↓ OR 600 800 350 1000 ns
SI↓ HF 340 410 180 510 ns
SO↓ Q 13 17 4 22 ns
SO↑
SO↓
SO↓ IR 600 800 350 1000 ns
SO↓ HF 340 410 170 510 ns
RST↓ OR 22 26 10 34 ns
RST↑ IR 12 18 5 22 ns
OE↑ Q 7 13 2 15 ns
OE↓ Q 6 12 2 13 ns
TO
(OUTPUT)
IR 12 18 5 22
Q 14 17 5 19
R1 = 500 Ω,
R2 = 500 Ω,
TA = 25°C
MIN TYP MAX MIN MAX
20 26 8 30
16 21 6 25
550 700 290 880
85 115 40 150
23 27 7 33
20 24 6 30
550 700 290 880
85 115 35 150
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
R1 = 500 Ω,
R2 = 500 Ω,
TA = MIN to MAX
SN74ALS235
UNIT
†
z
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SN74ALS235
64 × 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SDAS108A – OCTOBER 1986 – REVISED SEPTEMBER 1993
APPLICATION INFORMATION
HF
AF/AE
IR
SI
D0
D1
D2
D3
D4
HF
IR
SI
IR
SI
D0
D1
D2
D3
D4
HF
IR
SI
D0
D1
D2
D3
D4
RST
RST
RST
SO
OR
Q0
Q1
Q2
Q3
Q4
AF/AE
SO
OR
Q0
Q1
Q2
Q3
Q4
AF/AE
SO
OR
Q0
Q1
Q2
Q3
Q4
HF
IR
SI
D0
D1
D2
D3
D4
HF
IR
SI
D0
D1
D2
D3
D4
HF
IR
SI
D0
D1
D2
D3
D4
RST
RST
RST
AF/AE
SO
OR
Q0
Q1
Q2
Q3
Q4
AF/AE
SO
OR
Q0
Q1
Q2
Q3
Q4
AF/AE
SO
OR
Q0
Q1
Q2
Q3
Q4
HF
IR
SI
D0
D1
D2
D3
D4
HF
IR
SI
D0
D1
D2
D3
D4
HF
IR
SI
D0
D1
D2
D3
D4
RST
RST
RST
AF/AE
SO
OR
Q0
Q1
Q2
Q3
Q4
AF/AE
SO
OR
Q0
Q1
Q2
Q3
Q4
AF/AE
SO
OR
Q0
Q1
Q2
Q3
Q4
SO
OR
12
RST
Figure 8. 192-Word by 15-Bit Expansion
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SN74ALS235
64 × 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SDAS108A – OCTOBER 1986 – REVISED SEPTEMBER 1993
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT FOR 3-STATE OUTPUTS
Timing
Input
Data
Input
Input
(see Note B)
In-Phase
Output
Out-of-Phase
Output
7 V
S1
t
su
1.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.3 V
t
PLH
t
PHL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
Open
R1 = 500 Ω
1.3 V
1.3 V 1.3 V
R2 = 500 Ω
t
h
1.3 V
1.3 V
1.3 V1.3 V
Test Point
3.5 V
0.3 V
3.5 V
0.3 V
3.5 V
0.3 V
t
PHL
V
OH
V
OL
t
PLH
V
OH
V
OL
High-Level
Pulse
Low-Level
Pulse
Output
Control
Waveform 1
S1 Closed
(see Note C)
Waveform 2
S1 Open
(see Note C)
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
SWITCH POSITION TABLE
TEST S1
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
1.3 V
1.3 V
VOLTAGE WAVEFORMS
PULSE DURATION
1.3 V
t
PZL
1.3 V
t
t
PZH
VOLTAGE WAVEFORMS
PHZ
1.3 V
t
w
Open
Open
Open
Closed
Open
Closed
1.3 V
1.3 V
1.3 V
t
PLZ
V
0.3 V
3.5 V
0.3 V
3.5 V
0.3 V
3.5 V
0.3 V
3.5 V
OL
0.3 V
V
OH
0 V
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 2 ns, tf≤ 2 ns.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.
Figure 9. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SN74ALS235
64 × 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SDAS108A – OCTOBER 1986 – REVISED SEPTEMBER 1993
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 15
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. T esting and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MA Y INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
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BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
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intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
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