Page 1
INTEGRATED CIRCUITS
DATA SH EET
74AHC595; 74AHCT595
8-bit serial-in/serial or parallel-out
shift register with output latches;
3-state
Product specification
File under Integrated Circuits, IC06
2000 Mar 15
Page 2
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
FEATURES
• ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
CDM EIA/JESD22-C101 exceeds 1000 V
• Balanced propagation delays
• All inputs have Schmitt-trigger actions
• Inputs accept voltages higher than V
• For AHC only: operates with CMOS input levels
• For AHCT only: operates with TTL input levels
• Specified from −40 to +85 °C and from−40 to +125 °C.
APPLICATIONS
• Serial-to-parallel data conversion
• Remote control holding register.
CC
74AHC595; 74AHCT595
DESCRIPTION
The 74AHC/AHCT595 are high-speed Si-gate CMOS
devices and are pin compatible with Low power Schottky
TTL (LSTTL). They are specified in compliance with
JEDEC standard No. 7A.
The 74AHC/AHCT595 is an 8-stage serial shift register
with a storage register and 3-state outputs. The shift
register has separate clocks.
Data is shifted on the positive-going transitions of the
SHCPinput. The data in eachregisteris transferred to the
storage register on a positive-going transition of the ST
input. If both clocks are connected together, the shift
register will always be one clock pulse ahead of the
storage register.
The shift register has a serial input (DS) and a serial
standardoutput (Q7’)for cascading. It is alsoprovidedwith
asynchronous reset (active LOW) for all 8 shift register
stages. The storage register has 8 parallel 3-state bus
driver outputs. Data in the storage register appears at the
output whenever the output enable input (OE) is LOW.
CP
QUICK REFERENCE DATA
GND = 0 V; T
=25°C; tr=tf≤3.0 ns.
amb
SYMBOL PARAMETER CONDITIONS
t
PHL/tPLH
propagation delay CL= 15 pF; VCC=5V
SH
to Q7’ 4.0 3.8 ns
CP
ST
to Q
CP
n
MR to Q7’ 4.4 4.6 ns
C
f
C
I
max
PD
input capacitance 3.0 3.0 pF
maximum clock frequency 170 170 MHz
power dissipation capacitance CL= 50 pF; f = 1 MHz; notes 1, 2 and 3 180 190 pF
Notes
1. C
is used to determine the dynamic power dissipation (PDin µW).
PD
PD=CPD× V
2
× fi+ ∑ (CL× V
CC
2
× fo) where:
CC
fi= input frequency in MHz;
fo= output frequency in MHz;
∑ (CL× V
2
× fo) = sum of outputs;
CC
CL= output load capacitance in pF;
VCC= supply voltage in Volts.
2. The condition is VI= GND to VCC.
3. All 9 outputs switching.
TYPICAL
UNIT
AHC AHCT
4.2 4.0 ns
2000 Mar 15 2
Page 3
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift
74AHC595; 74AHCT595
register with output latches; 3-state
FUNCTION TABLE
See note 1.
INPUT OUTPUT
SH
CP
ST
OE MR D
CP
Q7’Q
S
n
X X L L X L NC a LOW level on MR only affects the shift registers
X ↑ L L X L L empty shift register loaded into storage register
X X H L X L Z shift register clear. Parallel outputs in high impedance
OFF-state.
↑ XLHHQ
’ NC logic HIGH level shifted into shift register stage 0.
6
Contents of all shift register stages shifted through, e.g.
previous state of stage 6 (internal Q6’) appears on the
serial output (Q7’).
X ↑ LHXNCQ
’ contents of shift register stages (internal Qn’) are
n
transferred to the storage register and parallel output
stages
↑↑LHXQ
’Q
6
’ contents of shift register shifted through. Previous
n
contents of the shift register is transferred to the storage
register and the parallel output stages.
FUNCTION
Note
1. H = HIGH voltage level;
L = LOW voltage level;
↑ = LOW-to-HIGH transition;
↓ = HIGH-to-LOW transition;
X = don’t care;
NC = no change;
Z = high impedance OFF-state.
ORDERING INFORMATION
PACKAGES
TYPE NUMBER
TEMPERATURE
RANGE
PINS PACKAGE MATERIAL CODE
74AHC595D −40 to +125 °C 16 SO plastic SOT109-1
74AHC595PW 16 TSSOP plastic SOT403-1
74AHCT595D 16 SO plastic SOT109-1
74AHCT595PW 16 TSSOP plastic SOT403-1
2000 Mar 15 3
Page 4
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift
74AHC595; 74AHCT595
register with output latches; 3-state
PINNING
PIN SYMBOL DESCRIPTION
1, 2, 3, 4, 5, 6, 7 and 15 Q
, Q2, Q3, Q4, Q5, Q6, Q7 and Q
1
8 GND ground (0 V)
9Q
10
11 SH
12 ST
13
14 D
16 V
’ serial data output
7
MR master reset (active LOW)
CP
CP
OE output enable input (active LOW)
S
CC
parallel data output
0
shift register clock input
storage register clock input
serial data input
DC supply voltage
handbook, halfpage
Q
Q
Q
Q
Q
Q
Q
GND
1
1
2
2
3
3
4
4
5
6
7
595
5
6
7
8
16
15
14
13
12
11
10
MNA551
Fig.1 Pin configuration.
handbook, halfpage
V
CC
Q
0
D
S
OE
ST
CP
SH
CP
MR
Q7'
9
14
SH
D
S
11 12
ST
CP
OEMR
CP
Q7'
Q
Q
Q
Q
Q
Q
Q
Q
1310
0
1
2
3
4
5
6
7
9
15
1
2
3
4
5
6
7
MNA552
Fig.2 Logic symbol.
2000 Mar 15 4
Page 5
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
handbook, halfpage
13
12
10
R
11
C1/
14
1D 2D
SRG8
EN3
C2
3
MNA553
15
1
2
3
4
5
6
7
9
handbook, halfpage
D
14
SH
11
MR
10
ST
12
13
OE
74AHC595; 74AHCT595
S
CP
8-STAGE SHIFT REGISTER
CP
8-BIT STORAGE REGISTER
3-STATE OUTPUTS
Q
Q
Q
Q
Q
Q
Q
0
151234567
3
2
1
6
4
5
Q7'
9
Q
7
MNA554
handbook, full pagewidth
D
S
SH
CP
MR
ST
CP
OE
Fig.3 IEC logic symbol.
STAGE 0 STAGES 1 TO 6 STAGE 7
DCPQ
FF0
R
DCPQ
LATCH
Fig.4 Functional diagram.
DQ
DCPQ
FF7
R
DCPQ
LATCH
Q
'
7
Q
0
Q
Q
1
2
Fig.5 Logic diagram.
2000 Mar 15 5
Q
Q
Q
3
Q
4
5
6
Q
MNA555
7
Page 6
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
handbook, full pagewidth
SH
ST
CP
D
CP
MR
OE
Q
Q
Q
Q
Q7’
S
0
1
6
7
74AHC595; 74AHCT595
Z-state
Z-state
Z-state
Z-state
MNA556
Fig.6 Timing diagram.
2000 Mar 15 6
Page 7
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift
74AHC595; 74AHCT595
register with output latches; 3-state
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER CONDITIONS
V
CC
V
I
V
O
T
amb
DC supply voltage 2.0 5.0 5.5 4.5 5.0 5.5 V
input voltage 0 − 5.5 0 − 5.5 V
output voltage 0 − V
operating ambient temperature see DCand AC
characteristics per
device
t
, t
r
f
input rise and fall ratios (∆t/∆V) VCC= 3.3 ±0.3 V −−100 −−−ns/V
=5±0.5 V −−20 −−20 ns/V
V
CC
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
CC
V
I
I
IK
I
OK
DC supply voltage −0.5 +7.0 V
input voltage −0.5 +7.0 V
DC input diode current VI< −0.5 V; note 1 −−20 mA
DC output clamping diode
−0.5 > VO>VCC+ 0.5 V; note 1 −±20 mA
current
I
O
I
CC
T
stg
P
D
DC output sink current −0.5 < VO<VCC+ 0.5 V −±25 mA
DC VCC or GND current −±75 mA
storage temperature −65 +150 °C
power dissipation per package for temperature range: −40 to +125 °C; note 2 − 500 mW
74AHC 74AHCT
UNIT
MIN. TYP. MAX. MIN. TYP. MAX.
0 − V
CC
CC
V
−40 +25 +85 −40 +25 +85 °C
−40 +25 +125 −40 +25 +125 °C
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. For SO packages: above 70 °C the value of P
derates linearly with 8 mW/K.
D
For TSSOP packages: above 60 °C the value of PDderates linearly with 5.5 mW/K.
2000 Mar 15 7
Page 8
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift
74AHC595; 74AHCT595
register with output latches; 3-state
DC CHARACTERISTICS
74AHC family
Over recommended operating conditions; voltages are referenced to GND (ground=0V).
amb
(°C)
SYMBOL PARAMETER
V
IH
HIGH-level input
voltage
V
IL
LOW-level input
voltage
V
OH
HIGH-level output
voltage
V
OL
LOW-level output
voltage
I
I
input leakage
current
I
OZ
3-state output
OFF-state current
I
CC
quiescent supply
current
C
I
input capacitance −−310−10 − 10 pF
TEST CONDITIONS T
25 −40 to +85 −40 to +125
OTHER VCC(V)
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
2.0 1.5 −−1.5 − 1.5 − V
3.0 2.1 −−2.1 − 2.1 − V
5.5 3.85 −−3.85 − 3.85 − V
2.0 −− 0.5 − 0.5 − 0.5 V
3.0 −− 0.9 − 0.9 − 0.9 V
5.5 −− 1.65 − 1.65 − 1.65 V
VI=VIHor VIL;
IO= −50 µA
2.0 1.9 2.0 − 1.9 − 1.9 − V
3.0 2.9 3.0 − 2.9 − 2.9 − V
4.5 4.4 4.5 − 4.4 − 4.4 − V
V
I=VIH
or VIL;
3.0 2.58 −−2.48 − 2.40 − V
IO= −4.0 mA
V
I=VIH
or VIL;
4.5 3.94 −−3.8 − 3.70 − V
IO= −8.0 mA
VI=VIHor VIL;
IO=50µA
2.0 − 0 0.1 − 0.1 − 0.1 V
3.0 − 0 0.1 − 0.1 − 0.1 V
4.5 − 0 0.1 − 0.1 − 0.1 V
V
I=VIH
or VIL;
3.0 −− 0.36 − 0.44 − 0.55 V
IO= 4.0 mA
V
I=VIH
or VIL;
4.5 −− 0.36 − 0.44 − 0.55 V
IO= 8.0 mA
VI=VCCor GND 5.5 −− 0.1 − 1.0 − 2.0 µA
VI=VIHor VIL;
5.5 −− ±0.25 −±2.5 −±10.0 µA
VO=VCCor GND
VI=VCCor GND;
5.5 −− 4.0 − 40 − 80 µA
IO=0
UNIT
2000 Mar 15 8
Page 9
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift
74AHC595; 74AHCT595
register with output latches; 3-state
74AHCT family
Over recommended operating conditions; voltages are referenced to GND (ground=0V).
SYMBOL PARAMETER
V
IH
HIGH-level input
voltage
V
IL
LOW-level input
voltage
V
OH
HIGH-level output
voltage
V
OL
LOW-level output
voltage
I
I
input leakage
current
I
OZ
3-state output
OFF-state current
I
CC
quiescent supply
current
∆I
CC
additional
quiescent supply
current per input
pin
C
I
input capacitance −−310−10 − 10 pF
TEST CONDITIONS T
25 −40 to +85 −40 to +125
OTHER VCC(V)
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
4.5 to 5.5 2.0 −−2.0 − 2.0 − V
4.5 to 5.5 −− 0.8 − 0.8 − 0.8 V
VI=VIHor VIL;
4.5 4.4 4.5 − 4.4 − 4.4 − V
IO= −50 µA
V
I=VIH
or VIL;
4.5 3.94 −−3.8 − 3.70 − V
IO= −8.0 mA
VI=VIHor VIL;
4.5 − 0 0.1 − 0.1 − 0.1 V
IO=50µA
V
I=VIH
or VIL;
4.5 −− 0.36 − 0.44 − 0.55 V
IO= 8.0 mA
VI=VIHor V
VI=VIHor VIL;
5.5 −− 0.1 − 1.0 − 2.0 µA
IL
5.5 −− ±0.25 −±2.5 −±10.0 µA
VO=VCCor GND
per input pin;
other inputs at
VCCor GND;
IO=0
VI=VCCor GND;
5.5 −− 4.0 − 40 − 80 µA
IO=0
VI=VCC− 2.1 V
4.5 to 5.5 −− 1.35 − 1.5 − 1.5 mA
other inputs at
VCCor GND;
IO=0
amb
(°C)
UNIT
2000 Mar 15 9
Page 10
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
AC CHARACTERISTICS
Type 74AHC595
GND = 0 V; tr=tf≤3.0 ns.
TEST CONDITIONS T
SYMBOL PARAMETER
VCC= 3.0 to 3.6 V; note 1
t
PHL/tPLH
propagation delay
SHCPto Q7’
propagation delay
ST
to Q
t
PHL
CP
propagation delay
n
MR to Q7’
t
PZH/tPZL
t
PHZ/tPLZ
t
PHL/tPLH
3-state output enable
time OE to Q
n
3-stateoutput disable
time OE to Q
n
propagation delay
SHCPto Q7’
propagation delay
ST
to Q
t
PHL
CP
propagation delay
n
MR to Q7’
t
PZH/tPZL
t
PHZ/tPLZ
t
W
3-state output enable
time OE to Q
n
3-stateoutput disable
time OE to Q
n
shiftclockpulsewidth
HIGH or LOW
storage clock pulse
width HIGH or LOW
master reset pulse
width LOW
t
su
set-up time
DSto SH
CP
set-up time
SH
to ST
t
t
f
h
rem
max
CP
hold time
DSto SH
removal time
MR to SH
maximumclockpulse
CP
CP
CP
frequency
SHCPor ST
CP
WAVEFORMS C
see Figs 7
15 pF − 5.7 13.0 1.0 15.0 1.0 16.5 ns
and 12
see Figs 8
and 12
see Figs 10
and 12
see Figs 11
and 12
see Figs 7
50 pF − 7.7 16.5 1.0 18.5 1.0 20.1 ns
and 12
see Figs 8
and 12
see Figs 10
and 12
see Figs 11
and 12
see Figs 7
and 12
see Figs 8
and 12
see Figs 10
and 12
see Figs 8
and 12
see Figs 9
and 12
see Figs 10
and 12
see Figs 7, 8
and 12
74AHC595; 74AHCT595
(°C)
amb
25 −40 to +85 −40 to +125
L
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
− 5.9 11.9 1.0 13.5 1.0 15.0 ns
− 5.9 12.8 1.0 13.7 1.0 15.0 ns
− 5.6 11.5 1.0 13.5 1.0 15.0 ns
− 5.4 11.0 1.0 13.0 1.0 14.5 ns
− 7.7 15.4 1.0 17.0 1.0 18.5 ns
− 7.4 16.3 1.0 17.2 1.0 18.7 ns
− 7.4 15.0 1.0 17.0 1.0 18.5 ns
− 8.7 15.7 1.0 16.2 1.0 17.5 ns
5.0 −−5.0 − 5.0 − ns
5.0 −−5.0 − 5.0 − ns
5.0 −−5.0 − 5.0 − ns
3.5 −−3.5 − 3.5 − ns
8.5 −−8.5 − 8.5 − ns
1.5 −−1.5 − 1.5 − ns
3.0 −−3.0 − 3.0 − ns
80 125 − 60 − 40 − MHz
UNIT
2000 Mar 15 10
Page 11
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
TEST CONDITIONS T
SYMBOL PARAMETER
= 4.5 to 5.5 V; note 2
V
CC
t
PHL/tPLH
propagation delay
SHCPto Q7’
propagation delay
ST
to Q
t
PHL
CP
propagation delay
n
MR to Q7’
t
PZH/tPZL
t
PHZ/tPLZ
t
PHL/tPLH
3-state output enable
OE to Q
time
n
3-stateoutput disable
time OE to Q
n
propagation delay
SHCPto Q7’
propagation delay
ST
to Q
t
PHL
CP
propagation delay
n
MR to Q7’
t
PZH/tPZL
t
PHZ/tPLZ
t
W
3-state output enable
time OE to Q
n
3-stateoutput disable
time OE to Q
n
shiftclockpulsewidth
HIGH or LOW
storage clock pulse
width HIGH or LOW
master reset pulse
width LOW
t
su
set-up time
DSto SH
CP
set-up time
SH
to ST
t
t
f
h
rem
max
CP
hold time
DSto SH
removal time
MR to SH
maximumclockpulse
CP
CP
CP
frequency
SHCPor ST
CP
Notes
1. Typical values at VCC= 3.3 V.
2. Typical values at VCC= 5.0 V.
WAVEFORMS C
see Figs 7
15 pF − 4.0 8.2 1.0 9.4 1.0 10.5 ns
and 12
see Figs 8
and 12
see Figs 10
and 12
see Figs 11
and 12
see Figs 7
50 pF − 5.4 10.0 1.0 11.4 1.0 12.5 ns
and 12
see Figs 8
and 12
see Figs 10
and 12
see Figs 11
and 12
see Figs 7
and 12
see Figs 8
and 12
see Figs 10
and 12
see Figs 8
and 12
see Figs 9
and 12
see Figs 10
and 12
see Figs 7, 8
and 12
74AHC595; 74AHCT595
(°C)
amb
25 −40 to +85 −40 to +125
L
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
− 4.2 7.4 1.0 8.5 1.0 9.5 ns
− 4.4 8.0 1.0 9.1 1.0 10.0 ns
− 4.0 8.6 1.0 10.0 1.0 11.0 ns
− 3.8 8.0 1.0 9.5 1.0 10.5 ns
− 5.5 9.0 1.0 10.5 1.0 11.5 ns
− 5.6 10.0 1.0 11.1 1.0 12.0 ns
− 5.3 10.6 1.0 12.0 1.0 13.0 ns
− 5.8 10.3 1.0 11.0 1.0 12.0 ns
5.0 −−5.0 − 5.0 − ns
5.0 −−5.0 − 5.0 − ns
5.0 −−5.0 − 5.0 − ns
3.0 −−3.0 − 3.0 − ns
5.0 −−5.0 − 5.0 − ns
2.0 −−2.0 − 2.0 − ns
2.5 −−2.5 − 2.5 − ns
130 170 − 110 − 90 − MHz
UNIT
2000 Mar 15 11
Page 12
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
Type 74AHCT595
GND = 0 V; tr=tf≤3.0 ns.
TEST CONDITIONS T
SYMBOL PARAMETER
VCC= 4.5 to 5.5 V; note 1
t
PHL/tPLH
propagation delay
SHCPto Q7’
propagation delay
to Q
ST
t
PHL
CP
propagation delay
n
MR to Q7’
t
PZH/tPZL
t
PHZ/tPLZ
t
PHL/tPLH
3-state output enable
time OE to Q
n
3-state output disable
time OE to Q
n
propagation delay
SHCPto Q7’
propagation delay
ST
to Q
t
PHL
CP
propagation delay
n
MR to Q7’
t
PZH/tPZL
t
PHZ/tPLZ
t
W
3-state output enable
time OE to Q
n
3-state output disable
time OE to Q
n
shift clock pulse width
HIGH or LOW
storage clock pulse
width HIGH or LOW
master reset pulse
width LOW
t
su
set-up time
SHCPto ST
CP
set-up time
D
to SH
t
t
f
h
rem
max
S
hold time
DSto SH
removal time
MR to SH
maximum clock pulse
CP
CP
CP
frequency
SHCPor ST
CP
WAVEFORMS C
see Figs 7
15 pF − 3.8 8.2 1.0 9.0 1.0 10.0 ns
and 12
see Figs 8
and 12
see Figs 10
and 12
see Figs 11
and 12
see Figs 7
50 pF − 5.2 10.0 1.0 11.0 1.0 12.0 ns
and 12
see Figs 8
and 12
see Figs 10
and 12
see Figs 11
and 12
see Figs 7
and 12
see Figs 8
and 12
see Figs 10
and 12
see Figs 8
and 12
see Figs 9
and 12
see Figs 10
and 12
see Figs 7, 8
and 12
74AHC595; 74AHCT595
(°C)
amb
25 −40 to +85 −40 to +125
L
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
− 4.0 7.4 1.0 8.5 1.0 9.5 ns
− 4.6 8.2 1.0 9.5 1.0 10.5 ns
− 4.8 9.0 1.0 11.0 1.0 12.0 ns
− 3.6 6.9 1.0 8.0 1.0 9.0 ns
− 5.3 9.0 1.0 10.5 1.0 11.5 ns
− 5.8 10.5 1.0 11.5 1.0 12.5 ns
− 6.2 11.6 1.0 13.0 1.0 14.5 ns
− 5.8 10.3 1.0 11.0 1.0 12.0 ns
5.0 −−5.0 − 5.0 − ns
5.0 −−5.0 − 5.0 − ns
5.0 −−5.0 − 5.0 − ns
5.0 −−5.0 − 5.0 − ns
3.0 −−3.0 − 3.0 − ns
2.0 −−2.0 − 2.0 − ns
3.0 −−3.0 − 3.0 − ns
130 170 − 110 − 90 − MHz
UNIT
Note
1. Typical values at V
= 5.0 V.
CC
2000 Mar 15 12
Page 13
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
AC WAVEFORMS
handbook, full pagewidth
V
I
SH
input
CP
GND
V
OH
Q7' output
V
OL
FAMILY
VI INPUT
REQUIREMENTS
AHC GND to V
CC
(1)
V
M
INPUT
50% VCC50% V
AHCT GND to 3.0 V 1.5 V 50% V
(1)
V
M
t
PLH
(2)
V
M
OUTPUT
74AHC595; 74AHCT595
1/f
max
t
W
t
PHL
(2)
V
M
MNA557
CC
CC
Fig.7 The clock (SHCP) to output (Q7’) propagation delays, the shift clock pulse width (tW) and maximum shift
clock frequency (f
handbook, full pagewidth
FAMILY
VI INPUT
REQUIREMENTS
AHC GND to V
AHCT GND to 3.0 V 1.5 V 50% V
SH
ST
Qn output
CC
).
max
V
input
CP
GND
V
input
CP
GND
V
OH
V
OL
INPUT
50% VCC50% V
I
(1)
V
M
t
su
I
(1)
V
M
t
W
t
PLH
(2)
V
M
(1)
V
M
(2)
V
M
1/f
max
t
PHL
MNA558
OUTPUT
CC
CC
Fig.8 The storage clock (STCP) to output (Qn) propagation delays, the storage clock pulse width (tW) and the
shift clock to storage clock set-up time (tsu).
2000 Mar 15 13
Page 14
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
handbook, full pagewidth
SHCP input
DS input
Q7' output
FAMILY
AHC GND to V
VI INPUT
REQUIREMENTS
CC
AHCT GND to 3.0 V 1.5 V 50% V
V
I
V
M
GND
V
I
GND
V
OH
V
OL
(1)
V
M
INPUT
V
M
OUTPUT
50% VCC50% V
(1)
(2)
CC
CC
74AHC595; 74AHCT595
t
su
t
h
(1)
V
M
(2)
V
M
The shaded areas indicatewhen the input is permitted to change for
predictable output performance.
t
su
t
h
MNA560
Fig.9 The data set-up (tsu) and hold (th) times for the DS input.
handbook, full pagewidth
FAMILY
REQUIREMENTS
AHC GND to V
MR input
SHCP input
Q7' output
VI INPUT
CC
V
I
GND
V
I
GND
V
OH
V
OL
(1)
V
M
INPUT
50% VCC50% V
AHCT GND to 3.0 V 1.5 V 50% V
(1)
V
M
t
t
PHL
(2)
V
M
OUTPUT
CC
CC
t
W
rem
(1)
V
M
(2)
V
M
MNA561
Fig.10 The master reset (MR) pulse width, the master reset to output (Q7’) propagation delays and the master
reset to shift clock (SHCP) removal time (t
rem
).
2000 Mar 15 14
Page 15
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
GND
V
CC
V
OL
V
OH
GND
V
I
(1)
V
M
t
PLZ
t
PHZ
outputs
enabled
handbook, full pagewidth
OE input
output
LOW-to-OFF
OFF-to-LOW
output
HIGH-to-OFF
OFF-to-HIGH
VOL + 0.3 V
VOH − 0.3 V
outputs
disabled
74AHC595; 74AHCT595
t
PZL
(2)
V
M
t
PZH
(2)
V
M
outputs
enabled
MNA450
FAMILY
VI INPUT
REQUIREMENTS
AHC GND to V
CC
(1)
V
M
INPUT
50% VCC50% V
AHCT GND to 3.0 V 1.5 V 50% V
Fig.11 3-state enable and disable times.
handbook, full pagewidth
PULSE
GENERATOR
V
OUTPUT
V
I
R
M
T
(2)
CC
CC
V
D.U.T.
CC
S1
V
CC
open
V
O
1000 Ω
C
L
MNA219
GND
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
open
V
CC
GND
Definitions for test circuit.
CL= load capacitance including jig and probe capacitance (See Chapter “AC characteristics”).
RT= termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig.12 Load circuitry for switching times.
2000 Mar 15 15
Page 16
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
PACKAGE OUTLINES
SO16: plastic small outline package; 16 leads; body width 3.9 mm
D
c
y
Z
16
9
74AHC595; 74AHCT595
SOT109-1
E
H
E
A
X
v M
A
pin 1 index
1
e
0 2.5 5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
mm
inches
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
A
A1A2A3b
max.
0.25
1.75
0.10
0.010
0.069
0.004
1.45
1.25
0.057
0.049
0.25
0.01
p
0.49
0.36
0.019
0.014
0.25
0.19
0.0100
0.0075
(1)E(1) (1)
cD
10.0
9.8
0.39
0.38
8
b
p
scale
eHELLpQZywv θ
4.0
1.27
3.8
0.16
0.050
0.15
w M
6.2
5.8
0.244
0.228
A
2
1.05
0.041
Q
A
1
detail X
1.0
0.7
0.4
0.6
0.028
0.039
0.020
0.016
(A )
L
p
L
0.25 0.1
0.25
0.01
0.01 0.004
A
3
θ
0.7
0.3
0.028
0.012
o
8
o
0
OUTLINE
VERSION
SOT109-1
IEC JEDEC EIAJ
076E07 MS-012
REFERENCES
2000 Mar 15 16
EUROPEAN
PROJECTION
ISSUE DATE
97-05-22
99-12-27
Page 17
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift
74AHC595; 74AHCT595
register with output latches; 3-state
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
E
H
E
16
D
c
y
Z
9
SOT403-1
A
X
v M
A
pin 1 index
18
w M
b
e
DIMENSIONS (mm are the original dimensions)
UNIT A
mm
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
A
max.
1.10
OUTLINE
VERSION
SOT403-1 MO-153
0.15
0.05
A2A
1
0.95
0.80
IEC JEDEC EIAJ
0.25
b
3
p
0.30
0.19
p
0 2.5 5 mm
scale
(1)E(2) (1)
cD
0.2
5.1
4.5
0.1
REFERENCES
4.9
4.3
0.65
eHELLpQZywv θ
A
6.6
6.2
Q
(A )
2
A
1
L
p
L
detail X
0.75
0.4
0.50
0.3
EUROPEAN
PROJECTION
3
A
θ
0.13 0.10.21.0
0.40
0.06
ISSUE DATE
95-04-04
99-12-27
o
8
o
0
2000 Mar 15 17
Page 18
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
SOLDERING
Introduction to soldering surface mount packages
Thistextgivesaverybriefinsight to a complex technology.
A more in-depth account of soldering ICs can be found in
our
“Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not alwayssuitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
tothe printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Wave soldering
Conventional single wave soldering is not recommended
forsurfacemountdevices(SMDs)orprinted-circuitboards
with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering
method was specifically developed.
74AHC595; 74AHCT595
If wave soldering is used the following conditions must be
observed for optimal results:
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
• Forpackageswithleadsonfoursides,thefootprintmust
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
2000 Mar 15 18
Page 19
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift
74AHC595; 74AHCT595
register with output latches; 3-state
Suitability of surface mount IC packages for wave and reflow soldering methods
PACKAGE
BGA, LFBGA, SQFP, TFBGA not suitable suitable
HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not suitable
(3)
PLCC
LQFP, QFP, TQFP not recommended
SSOP, TSSOP, VSO not recommended
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
, SO, SOJ suitable suitable
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
The package footprint must incorporate solder thieves downstream and at the side corners.
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”
WAVE REFLOW
(2)
SOLDERING METHOD
suitable
(3)(4)
(5)
suitable
suitable
(1)
.
DEFINITIONS
Data sheet status
Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
2000 Mar 15 19
Page 20
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© Philips Electronics N.V. SCA
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
2000
Internet: http://www.semiconductors.philips.com
69
Printed in The Netherlands 613507/01/pp20 Date of release: 2000 Mar 15 Document order number: 9397 750 06822
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