Page 1
INTEGRATED CIRCUITS
DATA SH EET
74AHC74; 74AHCT74
Dual D-type flip-flop with set and
reset; positive-edge trigger
Product specification
Supersedes data of 1999 Aug 05
File under Integrated Circuits, IC06
1999 Sep 23
Page 2
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
FEATURES
• ESD protection:
HBM EIA/JESD22-A114-A
exceeds 2000 V
MM EIA/JESD22-A115-A
exceeds 200 V
• Balanced propagation delays
• Inputsacceptsvoltageshigherthan
V
CC
• For AHC only:
operates with CMOS input levels
• For AHCT only:
operates with TTL input levels
• Output capability: standard
• ICC category: flip-flops
• Specified from
−40 to +85 and +125 °C.
DESCRIPTION
The 74AHC/AHCT74 are high-speed
Si-gate CMOS devices and are pin
compatible with low power Schottky
TTL (LSTTL). They are specified in
compliance with JEDEC standard
No. 7A.
The 74AHC/AHCT74 dual
positive-edge triggered, D-type
flip-flops with individual data (D)
inputs,clock (CP)inputs,set (SD)and
reset (RD) inputs; also
complementary Q and Q outputs.
The set and reset are asynchronous
active LOW inputs and operate
independently of the clock input.
Information on the data input is
transferred to the Q output on the
LOW-to-HIGH transition of the clock
pulse. The D inputs must be stable
one set-up time prior to the
LOW-to-HIGH clock transition for
predictable operation.
Schmitt-trigger action in the clock
input makes the circuit highly tolerant
to slower clock rise and fall times.
QUICK REFERENCE DATA
GND = 0 V; T
=25°C; tr=tf≤3.0 ns.
amb
SYMBOL PARAMETER CONDITIONS
t
PHL/tPLH
propagation delay CL= 15 pF;
nCP to nQ, n
n
SD,nRDto nQ, nQ 3.7 3.7 ns
f
max
C
C
I
PD
max. clock frequency 130 100 MHz
input capacitance VI=VCCor GND 4.0 4.0 pF
power dissipation
capacitance
Notes
1. C
is used to determine the dynamic power dissipation (PDin µW).
PD
PD=CPD× V
CC
fi= input frequency in MHz; fo= output frequency in MHz;
∑ (CL× V
2
× fo) = sum of outputs;
CC
CL= output load capacitance in pF;
VCC= supply voltage in Volts.
2. The condition is VI= GND to VCC.
FUNCTION TABLES
Table 1 See note 1
S
n
D
nR
LHXXHL
HLXXLH
LLXXHH
Table 2 See note 1
S
n
D
nR
HH↑LLH
HH↑HHL
Note to Tables 1 and 2
1. H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
↑ = LOW-to-HIGH CP transition;
= state after the next LOW-to-HIGH CP transition.
Q
n+1
74AHC74; 74AHCT74
TYPICAL
AHC AHCT
Q 3.7 3.3 ns
2
× fi+ ∑ (CL× V
INPUT OUTPUT
D
INPUT OUTPUT
D
VCC=5V
CL= 50 pF;
12 16 pF
f = 1 MHz;
notes 1 and 2
2
× fo) where:
CC
nCP nD nQ nQ
nCP nD nQ
n+1
nQ
UNIT
n+1
1999 Sep 23 2
Page 3
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
74AHC74; 74AHCT74
positive-edge trigger
ORDERING INFORMATION
OUTSIDE
NORTH
AMERICA
NORTH AMERICA
TEMPERATURE
RANGE
PINS PACKAGE MATERIAL CODE
74AHC74D 74AHC74D −40 to +85 °C 14 SO plastic SOT108-1
74AHC74PW 74AHC74PW DH 14 TSSOP plastic SOT402-1
74AHCT74D 74AHCT74D 14 SO plastic SOT108-1
74AHCT74PW 74AHCT74PW DH 14 TSSOP plastic SOT402-1
PINNING
PIN SYMBOL DESCRIPTION
1 and 13 1
RDand 2R
D
asynchronous reset-direct input (active LOW)
2 and 12 1D and 2D data inputs
3 and 11 1CPand 2CP clock input (LOW-to-HIGH, edge-triggered)
4 and 10 1
SDand 2S
D
asynchronous set-direct input (active LOW)
5 and 9 1Q and 2Q true flip-flop outputs
6 and 8 1
Q and 2Q complement flip-flop outputs
7 GND ground (0 V)
14 V
CC
DC supply voltage
PACKAGE
handbook, halfpage
1R
1D
1CP
1S
1Q
1Q
GND
1
D
2
3
4
D
74
5
6
7
MNA417
14
V
CC
13
2R
D
12
2D
11
2CP
2S
10
D
9
2Q
8
2Q
Fig.1 Pin configuration.
1999 Sep 23 3
handbook, halfpage
410
2S
1S
D
D
S
D
FF
R
D
2R
D
113
Q
Q
D
1Q
2Q
1Q
2Q
MNA418
2
1D
2D
1CP
2CP
D
CP
1R
12
3
11
Fig.2 Logic diagram.
5
9
6
8
Page 4
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
handbook, halfpage
4
S
3
C1
2
1D
1
R
10
S
11
C1
12
1D
13
R
MNA419
5
6
9
8
handbook, halfpage
74AHC74; 74AHCT74
1S
D
4
S
D
1D
2
D
1CP
CP
3
1R
D
1
2S
D
10
2D
12
11
13
2CP
2R
D
CP
D
1Q
Q
5
FF
1Q
6
Q
R
D
S
D
2Q
9
Q
FF
2Q
8
Q
R
D
MNA420
handbook, full pagewidth
D
R
D
S
D
CP
Fig.3 IEC logic symbol.
C
C
C
C
Fig.4 Functional diagram.
C
C
C
C
C
C
MNA421
Q
Q
Fig.5 Logic diagram (one flip-flop).
1999 Sep 23 4
Page 5
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
74AHC74; 74AHCT74
positive-edge trigger
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER CONDITIONS
V
CC
V
I
V
O
T
amb
DC supply voltage 2.0 5.0 5.5 4.5 5.0 5.5 V
input voltage 0 − 5.5 0 − 5.5 V
output voltage 0 − V
operating ambient temperature see DC and AC
characteristics per
device
t
(∆t/∆f) input rise and fall rates VCC= 3.3 V ±0.3 V −−100 −−−ns/V
r,tf
=5V±0.5 V −−20 −−20
V
CC
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground= 0 V).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
CC
V
I
I
IK
I
OK
I
O
I
CC
T
stg
P
D
DC supply voltage −0.5 +7.0 V
input voltage −0.5 +7.0 V
DC input diode current VI< −0.5 V; note 1 −−20 mA
DC output diode current VO< −0.5 Vor VO>VCC+ 0.5 V; note 1 −±20 mA
DC output source or sink current −0.5V<VO<VCC+ 0.5 V −±25 mA
DC VCC or GND current −±75 mA
storage temperature −65 +150 °C
power dissipation per package for temperature range: −40 to +85 °C; note 2 − 500 mW
74AHC 74AHCT
UNIT
MIN. TYP. MAX. MIN. TYP. MAX.
0 − V
CC
CC
V
−40 +25 +85 −40 +25 +85 °C
−40 +25 +125 −40 +25 +125 °C
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. For SO packages: above 70 °C the value of P
derates linearly with 8 mW/K.
D
For TSSOP packages: above 60 °C the value of PDderates linearly with 5.5 mW/K.
1999 Sep 23 5
Page 6
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
74AHC74; 74AHCT74
positive-edge trigger
DC CHARACTERISTICS
74AHC family
Over recommended operating conditions; voltage are referenced to GND (ground = 0 V).
SYMBOL PARAMETER
V
IH
HIGH-level input
voltage
V
IL
LOW-level input
voltage
V
OH
HIGH-level output
voltage; all
outputs
HIGH-level output
voltage
V
OL
LOW-level output
voltage; all
outputs
LOW-level output
voltage
I
I
input leakage
current
I
OZ
3-state output
OFF current
I
CC
quiescent supply
current
C
I
input capacitance −−310−10 − 10 pF
TEST CONDITIONS T
25 −40 to +85 −40 to +125
OTHER VCC(V)
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
2.0 1.5 −−1.5 − 1.5 − V
3.0 2.1 −−2.1 − 2.1 −
5.5 3.85 −−3.85 − 3.85 −
2.0 −− 0.5 − 0.5 − 0.5 V
3.0 −− 0.9 − 0.9 − 0.9
5.5 −− 1.65 − 1.65 − 1.65
VI=VIHor VIL;
IO= −50 µA
2.0 1.9 2.0 − 1.9 − 1.9 − V
3.0 2.9 3.0 − 2.9 − 2.9 −
4.5 4.4 4.5 − 4.4 − 4.4 −
V
I=VIH
or VIL;
3.0 2.58 −−2.48 − 2.40 − V
IO= −4.0 mA
V
I=VIH
or VIL;
4.5 3.94 −−3.8 − 3.70 −
IO= −8.0 mA
VI=VIHor VIL;
IO=50µA
2.0 − 0 0.1 − 0.1 − 0.1 V
3.0 − 0 0.1 − 0.1 − 0.1
4.5 − 0 0.1 − 0.1 − 0.1
V
I=VIH
or VIL;
3.0 −− 0.36 − 0.44 − 0.55 V
IO=4mA
V
I=VIH
or VIL;
4.5 −− 0.36 − 0.44 − 0.55
IO=8mA
VI=VCCor GND 5.5 −− 0.1 − 1.0 − 2.0 µA
VI=VIHor VIL;
5.5 −− ±0.25 −±2.5 −±10.0 µA
VO=VCCor GND
VI=VCCor GND;
5.5 −− 2.0 − 20 − 40 µA
IO=0
amb
(°C)
UNIT
1999 Sep 23 6
Page 7
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
74AHC74; 74AHCT74
positive-edge trigger
74AHCT family
Over recommended operating conditions; voltage are referenced to GND (ground = 0 V).
SYMBOL PARAMETER
V
IH
HIGH-level input
voltage
V
IL
LOW-level input
voltage
V
OH
HIGH-level output
voltage; all
outputs
HIGH-level output
voltage
V
OL
LOW-level output
voltage; all
outputs
LOW-level output
voltage
I
I
input leakage
current
I
OZ
3-state output
OFF current
I
CC
quiescent supply
current
∆I
CC
additional
quiescent supply
current per input
pin
C
I
input capacitance −−310−10 − 10 pF
TEST CONDITIONS T
25 −40 to +85 −40 to +125
OTHER VCC(V)
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
4.5 to 5.5 2.0 −−2.0 − 2.0 − V
4.5 to 5.5 −− 0.8 − 0.8 − 0.8 V
VI=VIHor VIL;
4.5 4.4 4.5 − 4.4 − 4.4 − V
IO= −50 µA
V
I=VIH
or VIL;
4.5 3.94 −−3.8 − 3.70 − V
IO= −8.0 mA
VI=VIHor VIL;
4.5 − 0 0.1 − 0.1 − 0.1 V
IO=50µA
V
I=VIH
or VIL;
4.5 −− 0.36 − 0.44 − 0.55 V
IO=8mA
VI=VIHor V
VI=VIHor VIL;
5.5 −− 0.1 − 1.0 − 2.0 µA
IL
5.5 −− ±0.25 −±2.5 −±10.0 µA
VO=VCCor GND
per input pin;
other inputs at
VCCor GND;
IO=0
VI=VCCor GND;
5.5 −− 2.0 − 20 − 40 µA
IO=0
VI=VCC− 2.1 V
4.5 to 5.5 −− 1.35 − 1.5 − 1.5 mA
other inputs at
VCCor GND;
IO=0
amb
(°C)
UNIT
1999 Sep 23 7
Page 8
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
AC CHARACTERISTICS
Type 74AHC74
GND = 0 V; tr=tf≤3.0 ns.
TEST CONDITIONS T
SYMBOL PARAMETER
VCC= 3.0 to 3.6 V; note 1
t
PHL/tPLH
propagation delay
nCP to nQ, nQ
propagation delay
n
SDnRDto nQ, nQ
f
max
maximum clock
pulse frequency
t
PHL/tPLH
propagation delay
nCP to nQ, nQ
propagation delay
n
SDnRDto nQ, nQ
t
W
clock pulse width
HIGH or LOW
set or reset pulse
width LOW
t
rem
removaltime set or
reset
t
su
set-up time
nD to nCP
t
h
hold time
nD to nCP
f
max
maximum clock
pulse frequency
WAVEFORMS C
see Figs 6 and 8 15 pF − 5.2 11.9 1.0 14.0 1.0 15.0 ns
see Figs 7 and 8 − 5.4 12.3 1.0 14.5 1.0 15.5 ns
see Figs 6 and 8 50 pF − 7.4 15.4 1.0 17.5 1.0 19.5 ns
see Figs 7 and 8 − 7.7 15.8 1.0 18.0 1.0 20.0 ns
see Figs 6 and 8 6.0 −−7.0 − 7.0 − ns
see Figs 7 and 8 6.0 −−7.0 − 7.0 − ns
see Figs 6 and 8 6.0 −−7.0 − 7.0 − ns
74AHC74; 74AHCT74
(°C)
amb
25 −40 to +85 −40 to +125
L
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
80 125 − 45 − 45 − ns
5.0 −−5.0 − 5.0 − ns
0.5 −−0.5 − 0.5 − ns
50 75 − 70 − 70 − ns
UNIT
1999 Sep 23 8
Page 9
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
TEST CONDITIONS T
SYMBOL PARAMETER
V
= 4.5 to 5.5 V; note 2
CC
t
PHL/tPLH
propagation delay
nCP to nQ, nQ
propagation delay
n
SDnRDto nQ, nQ
f
max
maximum clock
pulse frequency
t
PHL/tPLH
propagation delay
nCP to nQ, n
Q
propagation delay
n
SDto nQ, nQ
t
W
clock pulse width
HIGH or LOW
set or reset pulse
width LOW
t
rem
removaltime set or
reset
t
su
set-up time
nD to nCP
t
h
hold time
nD to nCP
f
max
maximum clock
pulse frequency
WAVEFORMS C
see Figs 6 and 8 15 pF − 3.7 7.3 1.0 8.5 1.0 9.5 ns
see Figs 7 and 8 − 3.7 7.7 1.0 9.0 1.0 10.0 ns
see Figs 6 and 8 50 pF − 5.2 9.3 1.0 10.5 1.0 12.0 ns
see Figs 7 and 8 − 5.3 9.7 1.0 11.0 1.0 12.5 ns
see Figs 6 and 8 5.0 −−5.0 − 5.0 − ns
see Figs 7 and 8 5.0 −−5.0 − 5.0 − ns
see Figs 6 and 8 5.0 −−5.0 − 5.0 − ns
74AHC74; 74AHCT74
(°C)
amb
25 −40 to +85 −40 to +125
L
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
130 170 − 110 − 110 − ns
3.0 −−3.0 − 3.0 − ns
0.5 −−0.5 − 0.5 − ns
90 115 − 75 − 75 − ns
UNIT
Notes
1. Typical values at VCC= 3.3 V.
2. Typical values at VCC= 5.0 V.
1999 Sep 23 9
Page 10
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
Type 74AHCT74
GND = 0 V; tr=tf≤3.0 ns.
TEST CONDITIONS T
SYMBOL PARAMETER
VCC= 4.5 to 5.5 V; note 1
t
PHL/tPLH
propagation delay
nCP to nQ, nQ
propagation delay
SDnRDto nQ, nQ
n
f
max
maximum clock
pulse frequency
t
PHL/tPLH
propagation delay
nCP to nQ, nQ
propagation delay
SDnRDto nQ, nQ
n
t
W
clock pulse width
HIGH or LOW
t
W(st)(rst)
set or reset pulse
width LOW
t
rem
removaltime set or
reset
t
su
set-up time
nD to nCP
t
h
hold time
nD to nCP
f
max
maximum clock
pulse frequency
WAVEFORMS C
see Figs 6 and 8 15 pF − 3.3 7.8 1.0 9.0 1.0 10.0 ns
see Figs 7 and 8 − 3.7 10.4 1.0 12.0 1.0 13.0 ns
see Figs 6 and 8 50 pF − 4.8 8.8 1.0 10.0 1.0 11.0 ns
see Figs 7 and 8 − 5.3 11.4 1.0 13.0 1.0 14.5 ns
see Figs 6 and 8 5.0 −−5.0 − 5.0 − ns
see Figs 7 and 8 5.0 −−5.0 − 5.0 − ns
see Figs 6 and 8 5.0 −−5.0 − 5.0 − ns
74AHC74; 74AHCT74
(°C)
amb
25 −40 to +85 −40 to +125
L
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
100 160 − 80 − 80 − ns
3.5 −−3.5 − 3.5 − ns
0 −−0−0−ns
80 140 − 65 − 65 − ns
UNIT
Note
1. Typical values at V
CC
= 5.0 V.
1999 Sep 23 10
Page 11
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
AC WAVEFORMS
GND
GND
V
OH
V
OL
V
OH
V
OL
V
I
(1)
V
M
t
su
V
I
t
PLH
handbook, full pagewidth
nD INPUT
nCP INPUT
nQ OUTPUT
nQ OUTPUT
74AHC74; 74AHCT74
t
h
1/f
max
(1)
V
M
t
W
t
PHL
(1)
V
M
(1)
V
M
t
t
su
PHL
t
h
t
PLH
MNA422
FAMILY
VI INPUT
REQUIREMENTS
AHC GND to V
CC
V
M
INPUT
50% V
(1)
CC
AHCT GND to 3.0 V 1.5 V 50% V
The shaded areas indicate when the input is permitted to change for predictable output performance.
(1)
V
M
OUTPUT
50% V
CC
CC
Fig.6 The clock (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the nD to nCP set-up, the
nCP to nD hold times, the output transition times and the maximum clock pulse frequency.
1999 Sep 23 11
Page 12
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
GND
GND
GND
V
OH
V
OL
V
OH
V
OL
V
I
V
I
(1)
V
M
t
W
V
I
t
PLH
(1)
V
M
(1)
V
M
t
PHL
handbook, full pagewidth
nCP INPUT
nSD INPUT
nRD INPUT
nQ OUTPUT
nQ OUTPUT
74AHC74; 74AHCT74
(1)
V
M
t
rem
t
W
(1)
V
M
t
PHL
t
PLH
MNA423
FAMILY
VI INPUT
REQUIREMENTS
AHC GND to V
CC
V
M
INPUT
50% V
(1)
CC
AHCT GND to 3.0 V 1.5 V 50% V
(1)
V
M
OUTPUT
50% V
CC
CC
Fig.7 The set (nSD) and reset (nRD) input to output (nQ, nQ) propagation delays, the set and reset pulse widths
and the nRDto nCP removal time.
1999 Sep 23 12
Page 13
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
handbook, full pagewidth
V
V
I
R
D.U.T.
T
TEST S
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
open
V
CC
GND
PULSE
GENERATOR
1
CC
74AHC74; 74AHCT74
S1
V
CC
open
GND
C
1000 Ω
L
MNA183
V
O
Fig.8 Load circuitry for switching times.
1999 Sep 23 13
Page 14
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
PACKAGE OUTLINES
SO14: plastic small outline package; 14 leads; body width 3.9 mm
D
c
y
Z
14
8
74AHC74; 74AHCT74
E
H
E
A
X
v M
A
SOT108-1
pin 1 index
b
4.0
3.8
0.16
0.15
7
w M
p
scale
eHELLpQZywv θ
1.27
0.050
1
e
0 2.5 5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
mm
inches
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
A
max.
1.75
0.069
A
1
0.25
0.10
0.010
0.004
A2A
1.45
1.25
0.057
0.049
0.25
0.01
b
3
p
0.49
0.25
0.36
0.19
0.019
0.0100
0.014
0.0075
(1)E(1)
cD
8.75
8.55
0.35
0.34
6.2
5.8
0.244
0.228
A
2
1.05
0.041
Q
A
1
detail X
1.0
0.7
0.4
0.6
0.028
0.039
0.024
0.016
(A )
L
p
L
0.25
0.01 0.004
A
3
θ
0.25 0.1
0.01
(1)
0.7
0.3
0.028
0.012
o
8
o
0
OUTLINE
VERSION
SOT108-1
IEC JEDEC EIAJ
076E06S MS-012AB
REFERENCES
1999 Sep 23 14
EUROPEAN
PROJECTION
ISSUE DATE
95-01-23
97-05-22
Page 15
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
74AHC74; 74AHCT74
positive-edge trigger
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
E
H
E
14
D
c
y
Z
8
SOT402-1
A
X
v M
A
pin 1 index
17
w M
b
e
DIMENSIONS (mm are the original dimensions)
UNIT A1A2A
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
A
max.
0.15
mm
1.10
OUTLINE
VERSION
SOT402-1 MO-153
0.05
0.95
0.80
IEC JEDEC EIAJ
0.25
b
3
p
0.30
0.19
p
0 2.5 5 mm
scale
(1)E(2) (1)
cD
0.2
5.1
0.1
4.9
REFERENCES
eHELLpQZywv θ
4.5
0.65
4.3
A
6.6
6.2
Q
(A )
2
A
1
L
L
detail X
0.75
0.4
0.50
0.3
EUROPEAN
PROJECTION
3
A
θ
p
0.13 0.10.21.0
0.72
0.38
ISSUE DATE
94-07-12
95-04-04
o
8
o
0
1999 Sep 23 15
Page 16
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
SOLDERING
Introduction to soldering surface mount packages
Thistext gives a verybriefinsight to a complextechnology.
A more in-depth account of soldering ICs can be found in
our
“Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface
mount IC packages.Wave soldering isnot alwayssuitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
tothe printed-circuit boardbyscreen printing, stencillingor
pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating,soldering andcooling) vary
between 100 and 200 seconds depending on heating
method.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Wave soldering
Conventional single wave soldering is not recommended
forsurfacemount devices (SMDs)orprinted-circuitboards
with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering
method was specifically developed.
74AHC74; 74AHCT74
If wave soldering is used the following conditions must be
observed for optimal results:
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
• Forpackageswith leads onfoursides,the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
During placement andbefore soldering,the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
1999 Sep 23 16
Page 17
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
74AHC74; 74AHCT74
positive-edge trigger
Suitability of surface mount IC packages for wave and reflow soldering methods
PACKAGE
BGA, SQFP not suitable suitable
HLQFP, HSQFP, HSOP, HTSSOP, SMS not suitable
(3)
PLCC
LQFP, QFP, TQFP not recommended
SSOP, TSSOP, VSO not recommended
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
5. Wave soldering is only suitable forSSOP andTSSOP packages with a pitch (e) equal to or larger than0.65 mm; it is
, SO, SOJ suitable suitable
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
The package footprint must incorporate solder thieves downstream and at the side corners.
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”
WAVE REFLOW
(2)
(3)(4)
(5)
SOLDERING METHOD
(1)
suitable
suitable
suitable
.
DEFINITIONS
Data sheet status
Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1999 Sep 23 17
Page 18
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
NOTES
74AHC74; 74AHCT74
1999 Sep 23 18
Page 19
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
NOTES
74AHC74; 74AHCT74
1999 Sep 23 19
Page 20
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© Philips Electronics N.V. SCA
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
1999
Internet: http://www.semiconductors.philips.com
68
Printed in The Netherlands 545002/02/pp20 Date of release: 1999 Sep 23 Document order number: 9397 750 06291
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