Datasheet 74AHC574, 74AHCT574 Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

74AHC574; 74AHCT574

Octal D-type flip-flop; positive
edge-trigger; 3-state

Product specification
File under Integrated Circuits, IC06

1999 Jun 16

Philips Semiconductors Product specification

Octal D-type flip-flop; positive edge-trigger; 3-state

FEATURES

• 3-state non-inverting outputs for
bus oriented applications

• 8-bit positive, edge-triggered
register

• ESD protection:
HBM EIA/JESD22-A114-A
exceeds 2000 V
MM EIA/JESD22-A115-A
exceeds 200 V

• Independent register and 3-state
buffer operation

• Common 3-state output enable
input

• Output capability; bus driver

category: MSI

• I

CC

• For AHC only:
operates with CMOS input levels

• For AHCT only:
operates with TTL input levels

• Specified from

−40 to +85 and +125 °C.

DESCRIPTION

The 74AHC/AHCT574 are high-speed Si-gate CMOS devices and are pin
compatible with low power Schottky TTL (LSTTL). They are specified in
compliance with JEDEC standard no. 7A.

The 74AHC/AHCT574 are octal D-type flip-flops featuring separate D-type
inputs for each flip-flop and 3-state outputs for bus oriented applications.
A clock (CP) and an output enable (

OE) input are common to all flip-flops.

The 8 flip-flops will store the state of their individual D-inputs that meet the
set-up and hold times requirements on the LOW-to-HIGH CP transition.

When OE is LOW the contents of the 8 flip-flops are available at the outputs.

OE is HIGH, the outputs go to the high-impedance OFF-state. Operation

When
of the OE input does not affect the state of the flip-flops.

The ‘574’ is functionally identical to the ‘564’, but has non-inverting outputs.
The ‘574’ is functionally identical to the ‘374’, but has a different pinning.

74AHC574;

74AHCT574

QUICK REFERENCE DATA

GND = 0 V; T

=25°C; tr=tf≤3.0 ns.

amb

SYMBOL PARAMETER CONDITIONS

t

PHL/tPLH

f

max

C

I

C

O

C

PD

propagation delay CL= 15 pF; VCC= 5 V 4.4 4.4 ns
CP to Q

n

maximum clock frequency CL= 15 pF; VCC= 5 V 130 130 MHz
input capacitance VI=VCCor GND 4.0 4.0 pF
output capacitance 4.0 4.0 pF
power dissipation

capacitance

CL= 50 pF; f = 1 MHz;
notes 1 and 2

Notes

1. C

is used to determine the dynamic power dissipation (PDin µW).

PD

PD=CPD× V

2

× fi+ ∑ (CL× V

CC

2

× fo) where:

CC

fi= input frequency in MHz;
fo= output frequency in MHz;
∑ (CL× V

2

× fo) = sum of outputs;

CC

CL= output load capacitance in pF;
VCC= supply voltage in Volts.

2. The condition is VI= GND to VCC.

TYPICAL

UNIT

AHC AHCT

10 12 pF

1999 Jun 16 2

Philips Semiconductors Product specification

Octal D-type flip-flop; positive edge-trigger; 3-state

74AHC574;

74AHCT574

FUNCTION TABLE

See note 1.

OPERATING MODES

INPUTS

OE CP D

n

INTERNAL

FLIP-FLOPS

Load and read register L ↑ IL L

L↑hH H

Load register and disable outputs H ↑ lL Z

H↑hH Z

Note

1. H = HIGH voltage level;

h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition;
L = LOW voltage level;
I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition;
Z = high-impedance OFF-state;
↑ = LOW-to-HIGH CP transition.

OUTPUTS

Q0to Q

7

ORDERING INFORMATION

OUTSIDE NORTH

AMERICA

NORTH AMERICA

PINS PACKAGE MATERIAL CODE

PACKAGES

74AHC574D 74AHC574D 20 SO plastic SOT163-1
74AHC574PW 74AHC574PW DH 20 TSSOP plastic SOT360-1
74AHCT574D 74AHCT574D 20 SO plastic SOT163-1
74AHCT574PW 74AHCT574PW DH 20 TSSOP plastic SOT360-1

PINNING

PIN SYMBOL DESCRIPTION

1 OE 3-state output enable input (active LOW)
2, 3, 4, 5, 6, 7, 8 and 9 D

0

to D

7

data inputs
10 GND ground (0 V)
11 CP clock input (LOW-to-HIGH, edge triggered)
19, 18, 17, 16, 15, 14, 13 and 12 Q
20 V

0
CC

to Q

7

3-state flip-flop outputs

DC supply voltage

1999 Jun 16 3

Philips Semiconductors Product specification

Octal D-type flip-flop; positive edge-trigger; 3-state

handbook, halfpage

OE

D
D
D
D
D
D
D
D

GND

1
2

0

3

1

4

2

5

3
4
5
6
7

574

6
7
8
9

10

MNA444

V

20

CC

Q

19

0

Q

18

1

Q

17

2

Q

16

3

Q

15

4

Q

14

5

Q

13

6

Q

12

7

CP

11

handbook, halfpage

74AHC574;

74AHCT574

11

2
3
4
5
6
7
8
9

CP

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D

7

OE

19

Q

0

18

Q

1

17

Q

2

16

Q

3

15

Q

4

14

Q

5

13

Q

6

12

Q

7

1

MNA445

handbook, halfpage

Fig.1 Pin configuration.

11

C1

1

EN

2

1D

3
4
5
6
7
8
9

MNA446

19

18
17
16
15
14
13
12

handbook, halfpage

2
3
4
5
6

7

8
9

11

1

Fig.2 Logic symbol.

D

0

D

1

D

2

D

3

FF1 to FF8

D

4

D

5

D

6

D

7

CP
OE

3-STATE

OUTPUTS

Q

0

Q

1

Q

2

Q

3

Q

4

Q

5

Q

6

Q

7

MNA447

19
18
17
16
15
14
13
12

Fig.3 IEC logic symbol.

1999 Jun 16 4

Fig.4 Functional diagram.

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1999 Jun 16 5

handbook, full pagewidth

Philips Semiconductors Product specification

Octal D-type flip-flop; positive edge-trigger; 3-state

CP

OE

D

0

D

FF1

CP

D

1

Q

D

FF2

CP

Q

0

D

2

Q DQ DQ DQ DQ DQ DQ

FF3

CP

Q

1

D

3

FF4

CP

Q

2

D

4

FF5

CP

Q

3

D

5

FF6

CP

Q

4

D

6

FF7

CP

Q

5

D

7

FF8

CP

Q

6

Q

MNA449

7

74AHCT574

74AHC574;

Fig.5 Logic diagram.

Philips Semiconductors Product specification

Octal D-type flip-flop; positive edge-trigger; 3-state

74AHC574;

74AHCT574

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER CONDITIONS

V

CC

V

I

V

O

T

amb

t

(∆t/∆f) input rise and fall

r,tf

DC supply voltage 2.0 5.0 5.5 4.5 5.0 5.5 V
input voltage 0 − 5.5 0 − 5.5 V
output voltage 0 − V
operating ambient

temperature range

see DC and AC
characteristics per device

VCC= 3.3 V ±0.3 V −−100 −−−ns/V
times except for
Schmitt-trigger

V

=5V±0.5 V −−20 −−20 ns/V

CC

inputs

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground = 0 V).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

CC

V

I

I

IK

I

OK

I

O

I

CC

T

stg

P

D

DC supply voltage −0.5 +7.0 V
input voltage range −0.5 +7.0 V
DC input diode current VI< −0.5 V; note 1 −−20 mA
DC output diode current VO< −0.5 V or VO>VCC+ 0.5 V; note 1 −±20 mA
DC output source or sink current −0.5V<VO<VCC+ 0.5 V −±25 mA
DC VCC or GND current −±75 mA
storage temperature range −65 +150 °C
power dissipation per package for temperature range: −40 to +125 °C;

note 2

74AHC 74AHCT

UNIT

MIN. TYP. MAX. MIN. TYP. MAX.

0 − V

CC

CC

V

−40 +25 +85 −40 +25 +85 °C

−40 +25 +125 −40 +25 +125 °C

− 500 mW

Notes

1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. For SO-packages: above 70 °C the value of P

derates linearly with 8 mW/K.

D

For TSSOP-packages: above 60 °C the value of PD derates linearly with 5.5 mW/K.

1999 Jun 16 6

Philips Semiconductors Product specification

Octal D-type flip-flop; positive edge-trigger; 3-state

DC CHARACTERISTICS
Family 74AHC

Over recommended operating conditions; voltage are referenced to GND (ground = 0 V).

SYMBOL PARAMETER

V

IH

HIGH-level input
voltage

V

IL

LOW-level input
voltage

V

OH

HIGH-level output
voltage; all
outputs

HIGH-level output
voltage

V

OL

LOW-level output
voltage; all
outputs

LOW-level output
voltage

I

I

input leakage
current

I

OZ

3-state output
OFF current

I

CC

quiescent supply
current

C

I

input capacitance −−310−10 − 10 pF

TEST CONDITIONS T

+25 −40 to +85 −40 to +125

OTHER VCC (V)

MIN. TYP. MAX. MIN. MAX. MIN. MAX.

2.0 1.5 −−1.5 − 1.5 − V

3.0 2.1 −−2.1 − 2.1 −

5.5 3.85 −−3.85 − 3.85 −

2.0 −− 0.5 − 0.5 − 0.5 V

3.0 −− 0.9 − 0.9 − 0.9

5.5 −− 1.65 − 1.65 − 1.65

VI=VIHor VIL;
IO= −50 µA

2.0 1.9 2.0 − 1.9 − 1.9 − V

3.0 2.9 3.0 − 2.9 − 2.9 −

4.5 4.4 4.5 − 4.4 − 4.4 −

V

I=VIH

or VIL;

3.0 2.58 −−2.48 − 2.40 − V

IO= −4.0 mA
V

I=VIH

or VIL;

4.5 3.94 −−3.8 − 3.70 −

IO= −8.0 mA
VI=VIHor VIL;

IO=50µA

2.0 − 0 0.1 − 0.1 − 0.1 V

3.0 − 0 0.1 − 0.1 − 0.1

4.5 − 0 0.1 − 0.1 − 0.1

V

I=VIH

or VIL;

3.0 −− 0.36 − 0.44 − 0.55 V

IO= 4.0 mA
V

I=VIH

or VIL;

4.5 −− 0.36 − 0.44 − 0.55

IO= 8.0 mA
VI=VCCor GND 5.5 −− 0.1 − 1.0 − 2.0 µA

VI=VIHor VIL;

5.5 −− ±0.25 −±2.5 −±10.0 µA

VO=VCCor GND
VI=VCCor GND;

5.5 −− 4.0 − 40 − 80 µA

IO=0

amb

(°C)

74AHC574;

74AHCT574

UNIT

1999 Jun 16 7

Philips Semiconductors Product specification

Octal D-type flip-flop; positive edge-trigger; 3-state

Family 74AHCT

Over recommended operating conditions; voltage are referenced to GND (ground = 0 V).

SYMBOL PARAMETER

V

IH

HIGH-level input
voltage

V

IL

LOW-level input
voltage

V

OH

HIGH-level
output voltage; all
outputs

HIGH-level
output voltage

V

OL

LOW-level output
voltage; all
outputs

LOW-level output
voltage

I

I

input leakage
current

I

OZ

3-state output
OFF current

I

CC

quiescent supply
current

∆I

CC

additional
quiescent supply
current per input
pin

C

I

input capacitance −−310−10 − 10 pF

TEST CONDITIONS T

+25 −40 to +85 −40 to +125

OTHER VCC (V)

MIN. TYP. MAX. MIN. MAX. MIN. MAX.

4.5 to 5.5 2.0 −− 2.0 − 2.0 − V

4.5 to 5.5 −−0.8 − 0.8 − 0.8 V

VI=VIHor VIL;

4.5 4.4 4.5 − 4.4 − 4.4 − V

IO= −50 µA

V

I=VIH

or VIL;

4.5 3.94 −− 3.8 − 3.70 − V

IO= −8.0 mA
VI=VIHor VIL;

4.5 − 0 0.1 − 0.1 − 0.1 V

IO=50µA

V

I=VIH

or VIL;

4.5 −−0.36 − 0.44 − 0.55 V

IO= 8.0 mA
VI=VIHor V

IL

VI=VIHor VIL;

5.5 −−0.1 − 1.0 − 2.0 µA

5.5 −−±0.25 −±2.5 −±10.0 µA
VO=VCCor GND
per input pin;
other inputs at
VCCor GND;
IO=0

VI=VCCor GND;

5.5 −−4.0 − 40 − 80 µA
IO=0

VI=VCC− 2.1 V

4.5 to 5.5 −−1.35 − 1.5 − 1.5 mA
other inputs at
VCCor GND;
IO=0

amb

74AHC574;

74AHCT574

(°C)

UNIT

1999 Jun 16 8

Philips Semiconductors Product specification

Octal D-type flip-flop; positive edge-trigger; 3-state

AC CHARACTERISTICS
Type 74AHC574

GND = 0 V; t

SYMBOL PARAMETER

t

PHL/tPLH

t

PZH/tPZL

t

PHZ/tPLZ

t

PHL/tPLH

t

PZH/tPZL

t

PHZ/tPLZ

t

PHL/tPLH

t

PZH/tPZL

t

PHZ/tPLZ

t

PHL/tPLH

t

PZH/tPZL

t

PHZ/tPLZ

≤3.0 ns.

r=tf

propagation
delay
CP to Q

n

3-state output
enable time
OE to Q

n

3-state output
disable time
OE to Q

n

propagation
delay
CP to Q

n

3-state output
enable time
OE to Q

n

3-state output
disable time
OE to Q

n

propagation
delay
CP to Q

n

3-state output
enable time
OE to Q

n

3-state output
disable time
OE to Q

n

propagation
delay
CP to Q

n

3-state output
enable time
OE to Q

n

3-state output
disable time
OE to Q

n

TEST CONDITIONS T

WAVEFORMS C

see Figs 6, 8

15 pF 3.0 to 3.6 − 6.5

L

VCC (V)

MIN. TYP. MAX. MIN. MAX. MIN. MAX.

and 9

see Figs 7

− 5.7

and 9

− 6.3

see Figs 6, 8

50 pF − 9.3

and 9

see Figs 7

− 8.2

and 9

− 9.1

see Figs 6, 8

15 pF 4.5 to 5.5 − 4.4

and 9

see Figs 7

− 4.2

and 9

− 4.3

see Figs 6, 8

50 pF − 6.2

and 9

see Figs 7

− 5.9

and 9

− 6.9

74AHC574;

74AHCT574

(°C)

amb

+25 −40 to +85 −40 to +125

(1)

13.2 1.0 15.5 1.0 16.5 ns

(1)

12.8 1.0 15.0 1.0 16.0 ns

(1)

13.0 1.0 15.0 1.0 16.5 ns

(1)

16.7 1.0 19.0 1.0 21.0 ns

(1)

16.3 1.0 18.5 1.0 20.5 ns

(1)

15.0 1.0 17.0 1.0 19.0 ns

(2)

8.6 1.0 10.0 1.0 11.0 ns

(2)

9.0 1.0 10.5 1.0 11.5 ns

(2)

9.0 1.0 10.5 1.0 11.5 ns

(2)

10.6 1.0 12.0 1.0 13.5 ns

(2)

11.0 1.0 12.5 1.0 14.0 ns

(2)

10.1 1.0 11.5 1.0 13.0 ns

UNIT

1999 Jun 16 9

Philips Semiconductors Product specification

Octal D-type flip-flop; positive edge-trigger; 3-state

TEST CONDITIONS T

SYMBOL PARAMETER

t

W

clock pulse
width
HIGH or LOW

t

su

setup time
Dnto CP

t

h

hold time
Dnto CP

f

max

maximum
clock pulse
frequency

t

W

clock pulse
width
HIGH or LOW

t

su

setup time
Dnto CP

t

h

hold time
Dnto CP

f

max

maximum
clock pulse
frequency

WAVEFORMS C

see Figs 6

50 pF 3.0 to 3.6 5.0 −−5.0 − 5.0 − ns

and 9

see Figs 8
and 9

see Figs 6
and 9

see Figs 6

15 pF 80 125 − 65 − 65 − MHz

50 pF 4.5 to 5.5 5.0 −−5.0 − 5.0 − ns

and 9

see Figs 8
and 9

see Figs 6
and 9

15 pF 130 180 − 110 − 110 − MHz

L

VCC (V)

MIN. TYP. MAX. MIN. MAX. MIN. MAX.

3.5 −−3.5 − 3.5 − ns

1.5 −−1.5 − 1.5 − ns

50 75 − 45 − 45 − MHz

3.0 −−3.0 − 3.0 − ns

1.5 −−1.5 − 1.5 − ns

85 115 − 75 − 75 − MHz

+25 −40 to +85 −40 to +125

amb

74AHC574;

74AHCT574

(°C)

UNIT

Notes

1. Typical values at VCC= 3.3 V.

2. Typical values at VCC= 5.0 V.

1999 Jun 16 10

Philips Semiconductors Product specification

Octal D-type flip-flop; positive edge-trigger; 3-state

Type 74AHCT574

GND = 0 V; t

SYMBOL PARAMETER

t

PHL/tPLH

t

PZH/tPZL

t

PHZ/tPLZ

t

PHL/tPLH

t

PZH/tPZL

t

PHZ/tPLZ

t

W

t

su

t

h

f

max

≤3.0 ns.

r=tf

propagation
delay
CP to Q

n

3-state output
enable time
OE to Q

n

3-state output
disable time
OE to Q

n

propagation
delay
CP to Q

n

3-state output
enable time
OE to Q

n

3-state output
disable time
OE to Q

n

clock pulse
width
HIGH or LOW

setup time
Dnto CP

hold time
Dnto CP

maximum
clock pulse
frequency

TEST CONDITIONS T

WAVEFORMS C

see Figs 6

15 pF 4.5 to 5.5 − 4.4

L

VCC (V)

MIN. TYP. MAX. MIN. MAX. MIN. MAX.

and 9

see Figs 7

− 4.3

and 9

− 4.3

see Figs 6

50 pF − 6.3

and 9

see Figs 7

− 6.1

and 9

− 6.2

see Figs 6

5.0 −−5.5 − 5.5 − ns

and 9

see Figs 8

3.0 −−3.5 − 3.5 − ns

and 9

1.5 −−1.5 − 1.5 − ns

see Figs 6
and 9

15 pF 130 180 − 110 − 110 − MHz

85 115 − 75 − 75 − MHz

74AHC574;

74AHCT574

(°C)

amb

+25 −40 to +85 −40 to +125

(1)

8.6 1.0 10.0 1.0 11.0 ns

(1)

9.0 1.0 10.5 1.0 11.5 ns

(1)

9.0 1.0 10.5 1.0 11.5 ns

(1)

10.6 1.0 12.0 1.0 13.5 ns

(1)

11.0 1.0 12.5 1.0 14.0 ns

(1)

10.1 1.0 11.5 1.0 13.0 ns

UNIT

Note

1. Typical values at V

CC

= 5.0 V.

1999 Jun 16 11

Philips Semiconductors Product specification

Octal D-type flip-flop; positive edge-trigger; 3-state

AC WAVEFORMS

handbook, full pagewidth

V

I

CP INPUT

GND

Qn OUTPUT

FAMILY

VI INPUT

REQUIREMENTS

AHC GND to V

CC

V

INPUT

50% V

M

CC

AHCT GND to 3.0 V 1.5 V 50% V

V

M

50% V

1/f

(1)

t

W

t

PHL

V

M

OUTPUT

CC
CC

V

max

M

(1)

t

PLH

74AHC574;

74AHCT574

MNA200

Fig.6 The clock (CP) to output (Qn) propagation delays.

handbook, full pagewidth

FAMILY

AHC GND to V

OE INPUT

OUTPUT
LOW-to-OFF
OFF-to-LOW

OUTPUT

HIGH-to-OFF
OFF-to-HIGH

VI INPUT

REQUIREMENTS

CC

V

I

GND

V

CC

V

OL

V

OH

GND

V

INPUT

50% V

M

CC

AHCT GND to 3.0 V 1.5 V 50% V

(1)

V

M

t

PLZ

t

PHZ

outputs

enabled

V

OUTPUT

50% V

M

CC
CC

VOL + 0.3 V

VOH − 0.3 V

outputs

disabled

t

PZL

t

PZH

V

M

V

M

outputs
enabled

MNA450

Fig.7 The 3-state enable and disable times.

1999 Jun 16 12

Philips Semiconductors Product specification

Octal D-type flip-flop; positive edge-trigger; 3-state

handbook, full pagewidth

CP INPUT

Dn INPUT

FAMILY

AHC GND to V

VI INPUT

REQUIREMENTS

CC

AHCT GND to 3.0 V 1.5 V 50% V

The shaded areas indicate when the input is permitted to change for predicable output performance.

V

GND

V

I

GND

V

INPUT

50% V

I

(1)

V

M

t

su

t

h

(1)

V

M

M

V

M

OUTPUT

50% V

CC

CC
CC

74AHC574;

74AHCT574

t

su

t

h

MNA448

handbook, full pagewidth

TEST S

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

open
V

CC

GND

Fig.8 The data set-up and hold times for Dn input.

V

CC

PULSE

GENERATOR

1

V

I

D.U.T.

R

T

FAMILY

REQUIREMENTS

AHC GND to V

V

O

VI INPUT

CC

C

L

MNA183

AHCT GND to 3.0 V 1.5 V 50% V

S

1000 Ω

V

INPUT

50% V

V

1

CC

open
GND

M

V

M

OUTPUT

50% V

CC

CC
CC

Fig.9 Load circuitry for switching times.

1999 Jun 16 13

Philips Semiconductors Product specification

Octal D-type flip-flop; positive edge-trigger; 3-state

PACKAGE OUTLINES

SO20: plastic small outline package; 20 leads; body width 7.5 mm

D

c

y

Z

20

11

74AHC574;

74AHCT574

SOT163-1

E

H

E

A

X

v M

A

pin 1 index

1

e

0 5 10 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

mm

A

max.

2.65

0.10

A

1

0.30

0.10

0.012

0.004

A2A

2.45

2.25

0.096

0.089

0.25

0.01

b

0.49

0.36

p

cD

0.32

0.23

0.013

0.009

3

0.019

0.014

UNIT

inches

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

10

w M

b

p

scale

(1)E(1) (1)

13.0

12.6

0.51

0.49

eHELLpQ

7.6

1.27

7.4

0.30

0.050

0.29

10.65

10.00

0.419

0.394

Q

A

2

A

1

1.4

0.055

1.1

0.4

0.043

0.016

detail X

1.1

1.0

0.043

0.039

(A )

L

p

L

0.25

0.01

A

3

θ

0.25 0.1

0.01

ywv θ

Z

0.9

0.4

0.035

0.004

0.016

o

8

o

0

OUTLINE
VERSION

SOT163-1

IEC JEDEC EIAJ

075E04 MS-013AC

REFERENCES

1999 Jun 16 14

EUROPEAN

PROJECTION

ISSUE DATE

95-01-24
97-05-22

Philips Semiconductors Product specification

Octal D-type flip-flop; positive edge-trigger; 3-state

TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm

E

H

E

20

D

c

y

Z

11

74AHC574;

74AHCT574

A

X

v M

A

SOT360-1

pin 1 index

110

w M

b

e

DIMENSIONS (mm are the original dimensions)

UNIT A1A2A

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

A

max.

0.15

mm

1.10

OUTLINE
VERSION

SOT360-1 MO-153AC

0.05

0.95

0.80

IEC JEDEC EIAJ

0.25

b

3

p

0.30

0.19

p

0 2.5 5 mm

scale

(1)E(2) (1)

cD

0.2

6.6

4.5

0.1

REFERENCES

6.4

4.3

0.65

eHELLpQZywv θ

A

6.6

6.2

Q

2

A

1

L

detail X

0.4

0.75

0.3

0.50

(A )

3

L

p

0.13 0.10.21.0

EUROPEAN

PROJECTION

A

θ

0.5

0.2

ISSUE DATE

93-06-16
95-02-04

o

8

o

0

1999 Jun 16 15

Philips Semiconductors Product specification

Octal D-type flip-flop; positive edge-trigger; 3-state

SOLDERING
Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface

mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.

• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Manual soldering

74AHC574;

74AHCT574

Wave soldering

Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

If wave soldering is used the following conditions must be
observed for optimal results:

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.

1999 Jun 16 16

Philips Semiconductors Product specification

Octal D-type flip-flop; positive edge-trigger; 3-state

74AHC574;

74AHCT574

Suitability of surface mount IC packages for wave and reflow soldering methods

PACKAGE

BGA, SQFP not suitable suitable
HLQFP, HSQFP, HSOP, SMS not suitable

(3)

PLCC
LQFP, QFP, TQFP not recommended
SSOP, TSSOP, VSO not recommended

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is

, SO, SOJ suitable suitable

temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

The package footprint must incorporate solder thieves downstream and at the side corners.

it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

WAVE REFLOW

(2)

(3)(4)
(5)

SOLDERING METHOD

(1)

suitable

suitable
suitable

.

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

1999 Jun 16 17

Philips Semiconductors Product specification

Octal D-type flip-flop; positive edge-trigger; 3-state

NOTES

74AHC574;

74AHCT574

1999 Jun 16 18

Philips Semiconductors Product specification

Octal D-type flip-flop; positive edge-trigger; 3-state

NOTES

74AHC574;

74AHCT574

1999 Jun 16 19

Philips Semiconductors – a worldwide company

Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. [phone], Fax. [phone]
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,

Tel. [phone], Fax. [phone]
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

220050 MINSK, Tel. [phone], Fax. [phone]

Belgium: see The Netherlands
Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

51 James Bourchier Blvd., 1407 SOFIA,
Tel. [phone], Fax. [phone]

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
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72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
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Colombia: see South America
Czech Republic: see Austria
Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V,

Tel. [phone], Fax. [phone]
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Indonesia: PT Philips Development Corporation, Semiconductors Division,
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Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. [phone], Fax. [phone]

Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
20124 MILANO, Tel. [phone], Fax. [phone]

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108-8507, Tel. [phone], Fax. [phone]

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Tel. [phone], Fax. [phone]

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. [phone], Fax. [phone]

Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. [phone], Fax [phone]

Middle East: see Italy

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]
Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]

Pakistan: see Singapore
Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. [phone], Fax. [phone]

Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. [phone], Fax. [phone]
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,

Tel. [phone], Fax. [phone]

Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 58088 Newville 2114,
Tel. [phone], Fax. [phone]

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04547-130 SÃO PAULO, SP, Brazil,
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Spain: Balmes 22, 08007 BARCELONA,
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Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. [phone] Fax. [phone]

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. [phone], Fax. [phone]

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. [phone], Fax. [phone]

Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,
ISTANBUL, Tel. [phone], Fax. [phone]

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone], Fax. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

© Philips Electronics N.V. SCA
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

1999 66

Internet: http://www.semiconductors.philips.com

Printed in The Netherlands 245002/01/pp20 Date of release: 1999Jun 16 Document order number: 9397 750 06027