Datasheet 74AHCT273, 74AHC273 Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

74AHC273; 74AHCT273

Octal D-type flip-flop with reset;
positive-edge trigger

Product specification
File under Integrated Circuits, IC06

1999 Sep 01

Philips Semiconductors Product specification

Octal D-type flip-flop with reset;
positive-edge trigger

FEATURES

• Ideal buffer for MOS microcontroller or memory

• Common clock and master reset

• ESD protection:

HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
CDM EIA/JESD22-C101 exceeds 1000 V

• Balanced propagation delays

• All inputs have Schmitt trigger actions

• Inputs accepts voltages higher than V

• See ‘377’ for clock enable version

• See ‘373’ for transparent latch version

• See ‘374’ for 3-state version

• For AHC only: operates with CMOS input levels

• For AHCT only: operates with TTL input levels

• Specified from −40 to +85 °C and −40 to +125 °C.

CC

74AHC273; 74AHCT273

DESCRIPTION

The 74AHC/AHCT273 are high-speed Si-gate CMOS
devices and are pin compatible with low power Schottky
TTL (LSTTL). They are specified in compliance with
JEDEC standard no. 7A.

The 74AHC/AHCT273 have eight edge-triggered, D-type
flip-flops with individual D inputs and Q outputs.

Thecommonclock(CP)andmasterreset(MR)inputsload
and reset (clear) all flip-flops simultaneously.

The state of each D input, one set-up time before the
LOW-to-HIGH clock transition, is transferred to the
corresponding output (Qn) of the flip-flop.

All outputs will be forced LOW independently of clock or
data inputs by a LOW on the MR input.

The device is useful for applications where the true output
only is required and the clock and master reset are
common to all storage elements.

QUICK REFERENCE DATA

Ground = 0 V; T

=25°C; tr=tf≤3.0 ns.

amb

SYMBOL PARAMETER CONDITIONS

t

PHL/tPLH

f

max

C

I

C

O

C

PD

propagation delay CL= 15 pF; VCC=5V

CP to Q
MR to Q

n

n

maximum clock frequency CL= 15 pF; VCC= 5 V 120 120 MHz
input capacitance VI=VCCor GND 3.0 3.0 pF
output capacitance 4.0 4.0 pF
power dissipation

capacitance

CL= 50 pF; f = 1 MHz;
notes 1 and 2

Notes

1. C

is used to determine the dynamic power dissipation (PDin µW).

PD

PD=CPD× V

2

× fi+ ∑ (CL× V

CC

2

× fo) where:

CC

fi= input frequency in MHz;
fo= output frequency in MHz;
∑ (CL× V

2

× fo) = sum of outputs;

CC

CL= output load capacitance in pF;
VCC= supply voltage in Volts.

2. The condition is VI= GND to VCC.

TYPICAL

UNIT

AHC AHCT

4.2 4.0 ns

3.7 3.9 ns

14.0 18.0 pF

1999 Sep 01 2

Philips Semiconductors Product specification

Octal D-type flip-flop with reset;

74AHC273; 74AHCT273

positive-edge trigger

FUNCTION TABLE

See note 1.

OPERATING MODES

MR CP D

reset (clear) L X X L
load ‘1’ H ↑ hL
load ‘0’ H ↑ lL

Note

1. H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
I = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
X = don’t care;
↑ = LOW-to-HIGH transition.

ORDERING INFORMATION

INPUTS OUTPUTS

n

Q

n

OUTSIDE NORTH

AMERICA

NORTH AMERICA

PINS PACKAGE MATERIAL CODE

PACKAGES

74AHC273D 74AHC273D 20 SO plastic SOT163-1
74AHC273PW 74AHC273PW DH 20 TSSOP plastic SOT360-1
74AHCT273D 74AHCT273D 20 SO plastic SOT163-1
74AHCT273PW 7AHCT273PW DH 20 TSSOP plastic SOT360-1

PINNING

PIN SYMBOL DESCRIPTION

1
2, 5, 6, 9, 12, 15, 16 and 19 Q
3, 4, 7, 8, 13, 14, 17 and 18 D

MR master reset input (active LOW)

0
0

to Q
to D

7

7

flip-flop outputs

data inputs
10 GND ground (0 V)
11 CP clock input (LOW-to-HIGH; edge-triggered)
20 V

CC

DC supply voltage

1999 Sep 01 3

Philips Semiconductors Product specification

Octal D-type flip-flop with reset;
positive-edge trigger

handbook, halfpage

MR

Q
D
D
Q
Q
D
D
Q

GND

1
2

0

3

0

4

1

5

1
2
2
3
3

273

6
7
8
9

10

MNA459

V

20

CC

Q

19

7

D

18

7

D

17

6

Q

16

6

Q

15

5

D

14

5

D

13

4

Q

12

4

CP

11

handbook, halfpage

74AHC273; 74AHCT273

11

CP

3

D

0

4

D

1

7

D

2

8

D

3

13

D

4

14

D

5

17

D

6

18

D

7

MR

1

Q
Q
Q
Q
Q
Q
Q
Q

0
1
2
3
4
5
6
7

MNA460

2
5
6

9
12
15
16
19

handbook, halfpage

Fig.1 Pin configuration.

11

C1

1

R

3

1D

4
7

8
13
14
17
18

MNA461

2

5
6

9
12
15
16
19

handbook, halfpage

Fig.2 Logic symbol.

D

3

0

D

1

4

D

7

2

D

8

D

13

D

14

D

17

D

18

MR

1

CP

11

FF1

3
4
5
6
7

to

FF8

Q
Q
Q
Q
Q
Q
Q
Q

MNA462

2

0

5

1

6

2

9

3

12

4

15

5

16

6

19

7

Fig.3 IEC logic symbol.

1999 Sep 01 4

Fig.4 Functional diagram.

Philips Semiconductors Product specification

Octal D-type flip-flop with reset;
positive-edge trigger

handbook, full pagewidth

CP

MR

D

0

D
CP

FF1

R

D

1

Q

D

D
CP

FF2

R

Q

0

D

2

Q

D

D
CP

FF3

R

Q

1

74AHC273; 74AHCT273

D

3

Q

D

D
CP

FF4

R

Q

2

D

4

Q

D

D
CP

FF5

R

Q

3

D

5

Q

D

D
CP

FF6

R

Q

4

D

6

Q

D

D
CP

FF7

R

Q

5

D

7

Q

D

D

Q

CP

FF8

R

D

Q

6

MNA463

Q

7

Fig.5 Logic diagram.

1999 Sep 01 5

Philips Semiconductors Product specification

Octal D-type flip-flop with reset;

74AHC273; 74AHCT273

positive-edge trigger

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER CONDITIONS

V

CC

V

I

V

O

T

amb

t

(∆t/∆f) input rise and fall ratio VCC= 3.3 ±0.3 V −−100 −−−ns/V

r,tf

DC supply voltage 2.0 5.0 5.5 4.5 5.0 5.5 V
input voltage 0 − 5.5 0 − 5.5 V
output voltage 0 − V
operating ambient

temperature

see DC and AC
characteristics per device

V

=5±0.5 V −−20 −−20

CC

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground= 0 V).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

CC

V

I

I

IK

I

OK

I

O

I

CC

T

stg

P

D

DC supply voltage −0.5 +7.0 V
input voltage −0.5 +7.0 V
DC input diode current VI< −0.5 V; note 1 −−20 mA
DC output diode current VO< −0.5 Vor VO>VCC+ 0.5 V; note 1 −±20 mA
DC output source or sink current −0.5V<VO<VCC+ 0.5 V −±25 mA
DC VCC or GND current −±75 mA
storage temperature −65 +150 °C
power dissipation per package for temperature range: −40 to +125 °C;

note 2

74AHC 74AHCT

UNIT

MIN. TYP. MAX. MIN. TYP. MAX.

0 − V

CC

CC

V

−40 +25 +85 −40 +25 +85 °C

−40 +25 +125 −40 +25 +125 °C

− 500 mW

Notes

1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. For SO package: above 70 °C the value of PD derates linearly with 8 mW/K.
For TSSOP package: above 60 °C the value of PD derates linearly with 5.5 mW/K.

1999 Sep 01 6

Philips Semiconductors Product specification

Octal D-type flip-flop with reset;

74AHC273; 74AHCT273

positive-edge trigger

DC CHARACTERISTICS
Family 74AHC

Over recommended operating conditions; voltage are referenced to GND (ground = 0 V).

SYMBOL PARAMETER

V

IH

HIGH-level input
voltage

V

IL

LOW-level input
voltage

V

OH

HIGH-level output
voltage; all outputs

HIGH-level output
voltage

V

OL

LOW-level output
voltage; all outputs

LOW-level output
voltage

I

I

input leakage
current

I

OZ

3-state output
OFF current

I

CC

quiescent supply
current

C

I

input capacitance −−310−10 − 10 pF

TEST CONDITIONS T

25 −40 to +85 −40 to +125

OTHER VCC (V)

MIN. TYP. MAX. MIN. MAX. MIN. MAX.

2.0 1.5 −−1.5 − 1.5 − V

3.0 2.1 −−2.1 − 2.1 −

5.5 3.85 −−3.85 − 3.85 −

2.0 −− 0.5 − 0.5 − 0.5 V

3.0 −− 0.9 − 0.9 − 0.9

5.5 −− 1.65 − 1.65 − 1.65

VI=VIHor VIL;
IO= −50 µA

2.0 1.9 2.0 − 1.9 − 1.9 − V

3.0 2.9 3.0 − 2.9 − 2.9 −

4.5 4.4 4.5 − 4.4 − 4.4 −

V

I=VIH

or VIL;

3.0 2.58 −−2.48 − 2.40 − V

IO= −4.0 mA
V

I=VIH

or VIL;

4.5 3.94 −−3.8 − 3.70 −

IO= −8.0 mA
VI=VIHor VIL;

IO=50µA

2.0 − 0 0.1 − 0.1 − 0.1 V

3.0 − 0 0.1 − 0.1 − 0.1

4.5 − 0 0.1 − 0.1 − 0.1

V

I=VIH

or VIL;

3.0 −− 0.36 − 0.44 − 0.55 V

IO= 4.0 mA
V

I=VIH

or VIL;

4.5 −− 0.36 − 0.44 − 0.55

IO= 8.0 mA
VI=VCCor GND 5.5 −− 0.1 − 1.0 − 2.0 µA

VI=VIHor VIL;

5.5 −− ±0.25 −±2.5 −±10.0 µA

VO=VCCor GND
VI=VCCor GND;

5.5 −− 4.0 − 40 − 80 µA

IO=0

amb

(°C)

UNIT

1999 Sep 01 7

Philips Semiconductors Product specification

Octal D-type flip-flop with reset;

74AHC273; 74AHCT273

positive-edge trigger

Family 74AHCT

Over recommended operating conditions; voltage are referenced to GND (ground = 0 V).

SYMBOL PARAMETER

V

IH

HIGH-level input
voltage

V

IL

LOW-level input
voltage

V

OH

HIGH-level
output voltage;
all outputs

HIGH-level
output voltage

V

OL

LOW-leveloutput
voltage; all
outputs

LOW-leveloutput
voltage

I

I

input leakage
current

I

OZ

3-state output
OFF current

I

CC

quiescent supply
current

∆I

CC

additional
quiescent supply
current per input
pin

C

I

input
capacitance

TEST CONDITIONS T

25 −40 to +85 −40 to +125

OTHER VCC (V)

MIN. TYP. MAX. MIN. MAX. MIN. MAX.

4.5 to 5.5 2.0 −−2.0 − 2.0 − V

4.5 to 5.5 −− 0.8 − 0.8 − 0.8 V

VI=VIHor VIL;

4.5 4.4 4.5 − 4.4 − 4.4 − V

IO= −50 µA

V

I=VIH

or VIL;

4.5 3.94 −−3.8 − 3.70 − V

IO= −8.0 mA
VI=VIHor VIL;

4.5 − 0 0.1 − 0.1 − 0.1 V

IO=50µA

V

I=VIH

or VIL;

4.5 −− 0.36 − 0.44 − 0.55 V

IO= 8.0 mA
VI=VIHor V

IL

VI=VIHor VIL;

5.5 −− 0.1 − 1.0 − 2.0 µA

5.5 −− ±0.25 −±2.5 −±10.0 µA
VO=VCCor GND
per input pin;
other inputs at
VCCor GND;
IO=0

VI=VCCor GND;

5.5 −− 4.0 − 40 − 80 µA
IO=0

VI=VCC− 2.1 V;

4.5 to 5.5 −− 1.35 − 1.5 − 1.5 mA
other inputs at
VCCor GND;
IO=0

−−310−10 − 10 pF

amb

(°C)

UNIT

1999 Sep 01 8

Philips Semiconductors Product specification

Octal D-type flip-flop with reset;
positive-edge trigger

AC CHARACTERISTICS
Type 74AHC273

Ground = 0 V; tr=tf≤3.0 ns.

TEST CONDITIONS T

SYMBOL PARAMETER

VCC= 3.0 to 3.6 V; note 1

t

PHL/tPLH

t

PHL

f

max

propagation delay
CP to Q

n

propagation delay
MR to Q

n

maximum clock
pulse frequency

t

PHL/tPLH

t

PHL

t

W

propagation delay
CP to Q

n

propagation delay
MR to Q

n

clock pulse width
HIGH or LOW

master reset
pulse width LOW

t

rem

removal time
MR to CP

t

su

set-up time
Dnto CP

t

h

hold time
Dnto CP

f

max

maximum clock
pulse frequency

WAVEFORMS C

see Figs 6 and 9 15 pF − 6.0 13.6 1.0 16.0 1.0 17.0 ns

see Figs 7 and 9 − 5.1 13.6 1.0 16.0 1.0 17.0 ns

see Figs 6 and 9 50 pF − 8.6 17.1 1.0 19.5 1.0 21.5 ns

see Figs 7 and 9 − 7.3 17.1 1.0 19.5 1.0 21.5 ns

see Figs 6 and 9 5.0 −−6.5 − 6.5 − ns

see Figs 7 and 9 5.0 −−6.0 − 6.0 − ns

see Figs 8 and 9 3.0 −−3.0 − 3.0 − ns

74AHC273; 74AHCT273

(°C)

amb

25 −40 to +85 −40 to +125

L

MIN. TYP. MAX. MIN. MAX. MIN. MAX.

75 120 − 65 − 65 − ns

2.5 −−2.5 − 2.5 − ns

1.0 −−1.0 − 1.0 − ns

50 75 − 45 − 45 − ns

UNIT

1999 Sep 01 9

Philips Semiconductors Product specification

Octal D-type flip-flop with reset;
positive-edge trigger

TEST CONDITIONS T

SYMBOL PARAMETER

V

= 4.5 to 5.5 V; note 2

CC

t

PHL/tPLH

t

PHL

f

max

propagation delay
CP to Q

n

propagation delay
MR to Q

n

maximum clock
pulse frequency

t

PHL/tPLH

t

PHL

t

W

propagation delay
CP to Q

n

propagation delay
MR to Q

n

clock pulse width
HIGH or LOW

master reset
pulse width LOW

t

rem

removal time
MR to CP

t

su

set-up time
Dnto CP

t

h

hold time
Dnto CP

f

max

maximum clock
pulse frequency

WAVEFORMS C

see Figs 6 and 9 15 pF − 4.2 9.0 1.0 10.5 1.0 11.5 ns

see Figs 7 and 9 − 3.7 8.5 1.0 10.0 1.0 11.0 ns

see Figs 6 and 9 50 pF − 6.0 11.0 1.0 12.5 1.0 14.0 ns

see Figs 7 and 9 − 5.3 10.5 1.0 12.0 1.0 13.5 ns

see Figs 6 and 9 5.0 −−5.0 − 5.0 − ns

see Figs 7 and 9 5.0 −−5.0 − 5.0 − ns

see Figs 8 and 9 3.0 −−3.0 − 3.0 − ns

74AHC273; 74AHCT273

(°C)

amb

25 −40 to +85 −40 to +125

L

MIN. TYP. MAX. MIN. MAX. MIN. MAX.

120 165 − 100 − 100 − ns

2.0 −−2.0 − 2.0 − ns

1.0 −−1.0 − 1.0 − ns

80 110 − 70 − 70 − ns

UNIT

Notes

1. Typical values at VCC= 3.3 V.

2. Typical values at VCC= 5.0 V.

1999 Sep 01 10

Philips Semiconductors Product specification

Octal D-type flip-flop with reset;
positive-edge trigger

Type 74AHCT273

Ground = 0 V; tr=tf≤3.0 ns.

TEST CONDITIONS T

SYMBOL PARAMETER

VCC= 4.5 to 5.5 V; note 1

t

PHL/tPLH

t

PHL

f

max

propagation delay
CP to Q

n

propagation delay
MR to Q

n

maximum clock
pulse frequency

t

PHL/tPLH

t

PHL

t

W

propagation delay
CP to Q

n

propagation delay
MR to Q

n

clock pulse width
HIGH or LOW

master reset
pulse width LOW

t

rem

removal time
MR to CP

t

su

setup time
Dnto CP

t

h

hold time
Dnto CP

f

max

maximum clock
pulse frequency

WAVEFORMS C

see Figs 6 and 9 15 pF − 4.0 7.5 1.0 8.8 1.0 9.5 ns

see Figs 7 and 9 − 3.9 10.0 1.0 11.6 1.0 12.5 ns

see Figs 6 and 9 50 pF − 5.8 9.2 1.0 10.5 1.0 11.5 ns

see Figs 7 and 9 − 5.6 11.0 1.0 12.6 1.0 14.0 ns

see Figs 6 and 9 5.0 −−6.5 − 6.5 − ns

see Figs 7 and 9 5.0 −−6.0 − 6.0 − ns

see Figs 8 and 9 3.0 −−3.0 − 3.0 − ns

74AHC273; 74AHCT273

(°C)

amb

25 −40 to +85 −40 to +125

L

MIN. TYP. MAX. MIN. MAX. MIN. MAX.

75 120 − 65 − 65 − ns

2.5 −−2.5 − 2.5 − ns

1.0 −−1.0 − 1.0 − ns

50 75 − 45 − 45 − ns

UNIT

Note

1. Typical values at V

CC

= 5.0 V.

1999 Sep 01 11

Philips Semiconductors Product specification

Octal D-type flip-flop with reset;
positive-edge trigger

AC WAVEFORMS

handbook, full pagewidth

V

I

CP INPUT

GND

Qn OUTPUT

FAMILY

AHC GND to V

VI INPUT

REQUIREMENTS

CC

AHCT GND to 3.0 V 1.5 V 50% V

V

INPUT

50% V

M

CC

(1)

V

M

t

W

t

PHL

V

OUTPUT

50% V

74AHC273; 74AHCT273

1/f

max

t

PLH

(1)

V

M

MNA200

M

CC
CC

Fig.6 The clock (CP) to output (Qn) propagation delays, the clock pulse width output transition times and the

maximum clock pulse frequency.

handbook, full pagewidth

MR INPUT

CP INPUT

Qn OUTPUT

FAMILY

AHC GND to V

VI INPUT

REQUIREMENTS

CC

AHCT GND to 3.0 V 1.5 V 50% V

V

GND

V

GND

V

GND

50% V

I

I

I

V

M

INPUT

CC

V

M

OUTPUT

50% V

V

CC
CC

(1)

M

t

PLH

t

W

t

rem

(1)

V

M

(1)

V

M

MNA464

Fig.7 The master reset (MR) pulse width, the master reset to output (Qn) propagation delays and master reset

to clock (CP) removal time.

1999 Sep 01 12

Philips Semiconductors Product specification

Octal D-type flip-flop with reset;
positive-edge trigger

handbook, full pagewidth

CP INPUT

Dn INPUT

Qn OUTPUT

FAMILY

AHC GND to V

VI INPUT

REQUIREMENTS

CC

AHCT GND to 3.0 V 1.5 V 50% V

V

GND

V

GND

50% V

I

I

V

M

INPUT

CC

(1)

V

M

OUTPUT

50% V

74AHC273; 74AHCT273

t

su

t

h

(1)

V

M

(1)

V

M

V

M

CC
CC

t

su

t

h

MNA202

The shaded areas indicate when the input is permitted to change for predicable output performance.

Fig.8 The data set-up and hold times for the data input (Dn).

handbook, full pagewidth

V

CC

TEST S

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

open
V

CC

GND

V

PULSE

GENERATOR

1

Definitions for test circuit.
CL= load capacitance including jig and probe capacitance (See Chapter “AC characteristics”).
RL= load resistance.
RT= termination resistance should be equal to the output impedance Zo of the pulse generator.

I

R

D.U.T.

T

V

O

C

L

1000 Ω

MNA183

S

V

1

CC

open
GND

Fig.9 Load circuitry for switching times.

1999 Sep 01 13

Philips Semiconductors Product specification

Octal D-type flip-flop with reset;
positive-edge trigger

PACKAGE OUTLINES

SO20: plastic small outline package; 20 leads; body width 7.5 mm

D

c

y

Z

20

11

74AHC273; 74AHCT273

SOT163-1

E

H

E

A

X

v M

A

pin 1 index

1

e

0 5 10 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

mm

A

max.

2.65

0.10

A

1

0.30

0.10

0.012

0.004

A2A

2.45

2.25

0.096

0.089

0.25

0.01

b

0.49

0.36

p

cD

0.32

0.23

0.013

0.009

3

0.019

0.014

UNIT

inches

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

10

w M

b

p

scale

(1)E(1) (1)

13.0

12.6

0.51

0.49

eHELLpQ

7.6

1.27

7.4

0.30

0.050

0.29

10.65

10.00

0.419

0.394

A

2

0.055

A

1.4

Q

1

detail X

1.1

1.1

1.0

0.4

0.043

0.043

0.039

0.016

(A )

L

p

L

0.25

0.01

A

3

θ

0.25 0.1

0.01

ywv θ

Z

0.9

0.4

8

0.004

0.035

0.016

0

o
o

OUTLINE
VERSION

SOT163-1

IEC JEDEC EIAJ

075E04 MS-013AC

REFERENCES

1999 Sep 01 14

EUROPEAN

PROJECTION

ISSUE DATE

95-01-24
97-05-22

Philips Semiconductors Product specification

Octal D-type flip-flop with reset;

74AHC273; 74AHCT273

positive-edge trigger

TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm

E

H

E

20

D

c

y

Z

11

SOT360-1

A

X

v M

A

pin 1 index

110

w M

b

e

DIMENSIONS (mm are the original dimensions)

UNIT A1A2A

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

A

max.

0.15

mm

1.10

OUTLINE
VERSION

SOT360-1 MO-153AC

0.05

0.95

0.80

IEC JEDEC EIAJ

0.25

b

3

p

0.30

0.19

p

0 2.5 5 mm

scale

(1)E(2) (1)

cD

0.2

6.6

4.5

0.1

REFERENCES

6.4

4.3

0.65

eHELLpQZywv θ

A

6.6

6.2

Q

2

A

1

L

detail X

0.75

0.4

0.50

0.3

(A )

3

L

p

0.13 0.10.21.0

EUROPEAN

PROJECTION

A

θ

0.5

0.2

ISSUE DATE

93-06-16
95-02-04

o

8

o

0

1999 Sep 01 15

Philips Semiconductors Product specification

Octal D-type flip-flop with reset;
positive-edge trigger

SOLDERING
Introduction to soldering surface mount packages

Thistextgives a very brief insight to a complextechnology.
A more in-depth account of soldering ICs can be found in
our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface

mount IC packages. Wavesoldering is notalways suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
tothe printed-circuit board by screenprinting,stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling)vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.

Wave soldering

Conventional single wave soldering is not recommended
forsurfacemountdevices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

74AHC273; 74AHCT273

If wave soldering is used the following conditions must be
observed for optimal results:

• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

– smaller than 1.27mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

• Forpackageswithleadson four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, thepackage must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Manual soldering

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.

1999 Sep 01 16

Philips Semiconductors Product specification

Octal D-type flip-flop with reset;

74AHC273; 74AHCT273

positive-edge trigger

Suitability of surface mount IC packages for wave and reflow soldering methods

PACKAGE

BGA, SQFP not suitable suitable
HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not suitable

(3)

PLCC
LQFP, QFP, TQFP not recommended
SSOP, TSSOP, VSO not recommended

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is

, SO, SOJ suitable suitable

temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

The package footprint must incorporate solder thieves downstream and at the side corners.

it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

WAVE REFLOW

(2)

SOLDERING METHOD

suitable

(3)(4)
(5)

suitable
suitable

(1)

.

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

1999 Sep 01 17

Philips Semiconductors Product specification

Octal D-type flip-flop with reset;
positive-edge trigger

74AHC273; 74AHCT273

NOTES

1999 Sep 01 18

Philips Semiconductors Product specification

Octal D-type flip-flop with reset;
positive-edge trigger

74AHC273; 74AHCT273

NOTES

1999 Sep 01 19

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For all other countries apply to: Philips Semiconductors,
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© Philips Electronics N.V. SCA
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

1999

Internet: http://www.semiconductors.philips.com

67

Printed in The Netherlands 245002/01/pp20 Date of release: 1999 Sep 01 Document order number: 9397 750 06158