Datasheet 74AHCT259, 74AHC259 Datasheet (Philips)

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Page 1

INTEGRATED CIRCUITS

DATA SH EET

74AHC259; 74AHCT259

8-bit addressable latch

Product speciﬁcation File under Integrated Circuits, IC06

2000 Mar 14

Page 2

Philips Semiconductors Product speciﬁcation

8-bit addressable latch

FEATURES

• ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1000 V

• Balanced propagation delays

• All inputs have Schmitt-trigger actions

• Combines demultiplexer and 8-bit latch

• Serial-to-parallel capability

• Output from each storage bit available

• Random (addressable) data entry

• Easily expandable

• Common reset input

• Useful as a 3-to-8 active HIGH decoder

• Inputs accept voltages higher than V

• For AHC only: operates with CMOS input levels

• For AHCT only: operates with TTL input levels

• Specified from −40 to +85 °C and from −40 to +125 °C.

74AHC259;

74AHCT259

DESCRIPTION

The 74AHC/AHCT259 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A.

The 74AHC/AHCT259 are high-speed 8-bit addressable latches designedfor general purpose storage applications in digital systems. The ‘259’ are multifunctional devices capable of storing single-line data in eight addressable latches, and also 3-to-8 decoder and demultiplexer, with active HIGH outputs (Q0 to Q7), functions are available.

The ‘259’ also incorporates an active LOW common reset (MR) for resetting all latches as well as an active LOW enable input (LE).

The ‘259’ has four modes of operation as shown in the mode select table. Inthe addressable latchmode, data on the data line (D) is written into the addressed latch. The addressed latch will follow the data input with all nonaddressed latches remaining in their previous states. In the memory mode, all latches remain in their previous states and are unaffected by the data or address inputs.

In the 3-to-8 decoding or demultiplexing mode, the addressed output follows the state of the (D) input with all other outputs in the LOW state. In the reset mode all outputs are LOW and unaffected by the address (A0 to A2) and data (D) input. When operating the ‘259’ as an address latch, changing more than one bit of the address could impose a transient-wrong address. Therefore, this should only be done while in the memory mode.

The mode select table summarizes the operations of the ‘259’.

2000 Mar 14 2

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Philips Semiconductors Product speciﬁcation

8-bit addressable latch

QUICK REFERENCE DATA

GND = 0 V; T

SYMBOL PARAMETER CONDITIONS

PHL/tPLH

Notes

1. C

is used to determine the dynamic power dissipation (PDin µW).

PD=CPD× V fi= input frequency in MHz; fo= output frequency in MHz; ∑ (CL× V CL= output load capacitance in pF; VCC= supply voltage in Volts.

2. The condition is VI= GND to VCC.

=25°C; tr=tf≤3.0 ns.

amb

propagation delay

DtoQn C

= 15 pF; VCC= 5 V 4.1 4.1 ns

An to Qn 5.3 5.5 ns LE to Qn 4.3 4.3 ns

MR to Qn 3.9 3.9 ns input capacitance VI=VCCor GND 3.0 3.0 pF output capacitance 4.0 4.0 pF power dissipation capacitance CL= 50 pF; f = 1 MHz; notes 1 and 2 13 17 pF

× fi+ ∑ (CL× V

× fo) = sum of outputs;

× fo) where:

74AHC259;

74AHCT259

TYPICAL

UNIT

AHC AHCT

2000 Mar 14 3

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Philips Semiconductors Product speciﬁcation

8-bit addressable latch

74AHC259;

74AHCT259

FUNCTION TABLE

See note 1.

OPERATING MODE

MR LEDA0A1A2Q0Q1Q2Q3Q4Q5Q6Q7

reset L H XXXX LLLLLLLL

demultiplexer (active HIGH 8-channel)

decoder (when D = H)

memory (do nothing) H H XXXXq

addressable latch H L

INPUTS OUTPUTS

dLLLQ=dLLLLLLL dHLLLQ=dLLLLLL dLHLLLQ=dLLLLL dHHLLLLQ=dLLLL dLLHLLLLQ=dLLL dHLHLLLLLQ=dLL dLHHLLLLLLQ=dL dHHHLLLLLLLQ=d

q1q2q3q4q5q6q

dLLLQ=dq dHLLq0Q=d q dLHLq0q1Q=d q dHHLq0q1q2Q=d q dLLHq0q1q2q3Q=d q dHLHq0q1q2q3q4Q=d q

q2q3q4q5q6q

4 4 4

5 5

6 6

dLHHq0q1q2q3q4q5Q=d q

7 7

HHHHq0q1q2q3q4q5q6Q=d

Note

1. H = HIGH voltage level; L = LOW voltage level; X = don’t care; d = HIGH or LOW data one set-up time prior to the LOW-to-HIGH LE transition; q = lower case letters indicate the state of the referenced output established during the last cycle in which it was

addressed or cleared.

ORDERING INFORMATION

PACKAGES

TYPE NUMBER

TEMPERATURE

RANGE

PINS PACKAGE MATERIAL CODE

74AHC259D −40 to +125 °C 16 SO plastic SOT109-1 74AHC259PW 16 TSSOP plastic SOT403-1 74AHCT259D 16 SO plastic SOT109-1 74AHCT259PW 16 TSSOP plastic SOT403-1

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Philips Semiconductors Product speciﬁcation

8-bit addressable latch

PINNING

PIN SYMBOL DESCRIPTION

1, 2 and 3 A0, A1 and A2 address input 4, 5, 6, 7, 9, 10, 11 and 12 Q0 to Q7 latch outputs 8 GND ground (0 V) 13 D data input 14 15 16 V

handbook, halfpage

A1 A2

Q1 Q2 Q3

GND

1 2 3 4

259

5 6 7 8

MNA574

LE latch enable input (active LOW) MR conditional reset input (active LOW)

LE D

13 12

Q6 Q5

handbook, halfpage

DC supply voltage

74AHC259;

74AHCT259

MNA573

Fig.1 Pin configuration.

2000 Mar 14 5

Fig.2 Logic symbol.

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Philips Semiconductors Product speciﬁcation

8-bit addressable latch

handbook, halfpage

1 2 3

G10

9,10D

1 2 3 4 5 6 7

74AHC259;

74AHCT259

handbook, halfpage

C10

MNA572

5 6 7

9 10 11 12

2 3

14 15 13

LE MR D

1-of-8

DECODER

8 LATCHES

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

MNA571

4 5 6 7

9 10 11 12

Fig.3 IEC logic symbol.

OPERATING MODE SELECT TABLE

LE MR MODE

L H addressable latch

H H memory

L L active HIGH 8-channel demultiplexer

H L reset

Note

1. H = HIGH voltage level; L = LOW voltage level.

Fig.4 Functional diagram.

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Philips Semiconductors Product speciﬁcation

8-bit addressable latch

74AHC259;

74AHCT259

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER CONDITIONS

amb

DC supply voltage 2.0 5.0 5.5 4.5 5.0 5.5 V input voltage 0 − 5.5 0 − 5.5 V output voltage 0 − V operating ambient temperature see DC and AC

characteristics per device

, t

input rise and fall ratios (∆t/∆f) VCC= 3.3 ±0.3 V −−100 −−−ns/V

=5±0.5 V −−20 −−20 ns/V

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referencedto GND (ground = 0 V).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

stg

DC supply voltage −0.5 +7.0 V input voltage −0.5 +7.0 V DC input diode current VI< −0.5 V; note 1 −−20 mA DC output clamping diode current VO< −0.5 Vor VO>VCC+ 0.5 V; note 1 −±20 mA DC output sink current −0.5V<VO<VCC+ 0.5 V −±25 mA DC VCC or GND current −±75 mA storage temperature −65 +150 °C power dissipation per package for temperature range: −40 to +125 °C; note 2 − 500 mW

74AHC 74AHCT

UNIT

MIN. TYP. MAX. MIN. TYP. MAX.

0 − V

−40 +25 +85 −40 +25 +85 °C

−40 +25 +125 −40 +25 +125 °C

Notes

1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. For SO packages: above 70 °C the value of P

derates linearly with 8 mW/K.

For TSSOP packages: above 60 °C the value of PDderates linearly with 5.5 mW/K.

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Philips Semiconductors Product speciﬁcation

8-bit addressable latch

DC CHARACTERISTICS 74AHC family

Over recommended operating conditions; voltages are referenced to GND (ground=0V).

amb

(°C)

SYMBOL PARAMETER

HIGH-level input voltage

LOW-level input voltage

HIGH-level output voltage

LOW-level output voltage

input leakage current

3-state output OFF-state current

quiescent supply current

input capacitance −−310−10 − 10 pF

TEST CONDITIONS T

25 −40 to +85 −40 to +125

OTHER VCC(V)

MIN. TYP. MAX. MIN. MAX. MIN. MAX.

2.0 1.5 −−1.5 − 1.5 − V

3.0 2.1 −−2.1 − 2.1 − V

5.5 3.85 −−3.85 − 3.85 − V

2.0 −− 0.5 − 0.5 − 0.5 V

3.0 −− 0.9 − 0.9 − 0.9 V

5.5 −− 1.65 − 1.65 − 1.65 V

VI=VIHor VIL; IO= −50 µA

2.0 1.9 2.0 − 1.9 − 1.9 − V

3.0 2.9 3.0 − 2.9 − 2.9 − V

4.5 4.4 4.5 − 4.4 − 4.4 − V

I=VIH

or VIL;

3.0 2.58 −−2.48 − 2.40 − V

IO= −4.0 mA V

I=VIH

or VIL;

4.5 3.94 −−3.8 − 3.70 − V

IO= −8.0 mA VI=VIHor VIL;

IO=50µA

2.0 − 0 0.1 − 0.1 − 0.1 V

3.0 − 0 0.1 − 0.1 − 0.1 V

4.5 − 0 0.1 − 0.1 − 0.1 V

I=VIH

or VIL;

3.0 −− 0.36 − 0.44 − 0.55 V

IO= 4.0 mA V

I=VIH

or VIL;

4.5 −− 0.36 − 0.44 − 0.55 V

IO= 8.0 mA VI=VCCor GND 5.5 −− 0.1 − 1.0 − 2.0 µA

VI=VIHor VIL;

5.5 −− ±0.25 −±2.5 −±10.0 µA

VO=VCCor GND VI=VCCor GND;

5.5 −− 4.0 − 40 − 80 µA

IO=0

74AHC259;

74AHCT259

UNIT

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Philips Semiconductors Product speciﬁcation

8-bit addressable latch

74AHCT family

Over recommended operating conditions; voltages are referenced to GND (ground=0V).

SYMBOL PARAMETER

HIGH-level input voltage

LOW-level input voltage

HIGH-level output voltage

LOW-level output voltage

input leakage current

3-state output OFF-state current

quiescent supply current

∆I

additional quiescent supply current per input pin

input capacitance −−310−10 − 10 pF

TEST CONDITIONS T

25 −40 to +85 −40 to +125

OTHER VCC(V)

MIN. TYP. MAX. MIN. MAX. MIN. MAX.

4.5 to 5.5 2.0 −−2.0 − 2.0 − V

4.5 to 5.5 −− 0.8 − 0.8 − 0.8 V

VI=VIHor VIL;

4.5 4.4 4.5 − 4.4 − 4.4 − V

IO= −50 µA V

I=VIH

or VIL;

4.5 3.94 −−3.8 − 3.70 − V

IO= −8.0 mA VI=VIHor VIL;

4.5 − 0 0.1 − 0.1 − 0.1 V

IO=50µA V

I=VIH

or VIL;

4.5 −− 0.36 − 0.44 − 0.55 V

IO= 8.0 mA VI=VIHor V

VI=VIHor VIL;

5.5 −− 0.1 − 1.0 − 2.0 µA

5.5 −− ±0.25 −±2.5 −±10.0 µA VO=VCCor GND per input pin; other inputs at VCCor GND; IO=0

VI=VCCor GND;

5.5 −− 4.0 − 40 − 80 µA IO=0

VI=VCC− 2.1 V

4.5 to 5.5 −− 1.35 − 1.5 − 1.5 mA other inputs at VCCor GND; IO=0

amb

(°C)

74AHC259;

74AHCT259

UNIT

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Philips Semiconductors Product speciﬁcation

8-bit addressable latch

AC CHARACTERISTICS Type 74AHC259

GND = 0 V; tr=tf≤3.0 ns.

SYMBOL PARAMETER

VCC= 3.0 to 3.6 V; note 1

PHL/tPLH

PHL

PHL/tPLH

PHL

propagation delay DtoQn

propagation delay An to Qn

propagation delay LE to Qn

propagation delay MR to Qn

propagation delay DtoQn

propagation delay An to Qn

propagation delay LE to Qn

propagation delay MR to Qn

LE pulse width HIGH or LOW

MR pulse width LOW

set-up time DtoLE, An to LE

hold time D to LE, An to LE

74AHC259;

74AHCT259

TEST CONDITIONS T

25 −40 to +85 −40 to +125

WAVEFORMS C

MIN. TYP. MAX. MIN. MAX. MIN. MAX.

see Figs 5 and 11 15 pF − 5.8 11.5 1.0 13.5 1.0 15.0 ns

see Figs 6 and 11 − 7.5 14.5 1.0 17.0 1.0 18.5 ns

see Figs 7 and 11 − 6.2 12.0 1.0 14.0 1.0 15.2 ns

see Figs 8 and 11 − 5.4 10.5 1.0 12.5 1.0 13.5 ns

see Figs 5 and 11 50 pF − 7.3 14.5 1.0 17.0 1.0 18.5 ns

see Figs 6 and 11 − 9.1 18.0 1.0 21.0 1.0 23.0 ns

see Figs 7 and 11 − 7.7 15.5 1.0 17.5 1.0 19.0 ns

see Figs 8 and 11 − 7.0 13.5 1.0 15.5 1.0 17.0 ns

see Figs 7 and 11 5.0 −−5.0 − 5.0 − ns

see Figs 8 and 11 5.0 −−5.0 − 5.0 − ns

see Figs 9,

4.0 −−4.0 − 4.0 − ns

10 and 11 see Figs 9 and 11 1.0 −−1.0 − 1.0 − ns

amb

(°C)

UNIT

2000 Mar 14 10

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Philips Semiconductors Product speciﬁcation

8-bit addressable latch

SYMBOL PARAMETER

= 4.5 to 5.5 V; note 2

PHL/tPLH

PHL

PHL/tPLH

PHL

propagation delay DtoQn

propagation delay An to Qn

propagation delay LE to Qn

propagation delay MR to Qn

propagation delay DtoQn

propagation delay An to Qn

propagation delay LE to Qn

propagation delay MR to Qn

LE pulse width HIGH or LOW

MR pulse width LOW

set-up time DtoLE, An to LE

hold time D to LE, An to LE

74AHC259;

74AHCT259

TEST CONDITIONS T

25 −40 to +85 −40 to +125

WAVEFORMS C

MIN. TYP. MAX. MIN. MAX. MIN. MAX.

see Figs 5 and 11 15 pF − 4.1 7.5 1.0 9.0 1.0 10.0 ns

see Figs 6 and 11 − 5.3 9.5 1.0 11.5 1.0 12.5 ns

see Figs 7 and 11 − 4.3 8.0 1.0 9.5 1.0 10.5 ns

see Figs 8 and 11 − 3.9 7.0 1.0 8.5 1.0 9.5 ns

see Figs 5 and 11 50 pF − 5.3 9.5 1.0 11.0 1.0 12.0 ns

see Figs 6 and 11 − 6.5 11.5 1.0 13.5 1.0 15.0 ns

see Figs 7 and 11 − 5.5 10.0 1.0 11.5 1.0 12.5 ns

see Figs 8 and 11 − 5.1 9.0 1.0 10.5 1.0 11.5 ns

see Figs 7 and 11 5.0 −−5.0 − 5.0 − ns

see Figs 8 and 11 5.0 −−5.0 − 5.0 − ns

see Figs 9,

4.0 −−4.0 − 4.0 − ns

10 and 11 see Figs 9 and 11 1.0 −−1.0 − 1.0 − ns

amb

(°C)

UNIT

Notes

1. Typical values at VCC= 3.3 V.

2. Typical values at VCC= 5.0 V.

2000 Mar 14 11

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Philips Semiconductors Product speciﬁcation

8-bit addressable latch

Type 74AHCT259

GND = 0 V; tr=tf≤3.0 ns.

SYMBOL PARAMETER

VCC= 4.5 to 5.5 V; note 1

PHL/tPLH

PHL

PHL/tPLH

PHL

propagationdelay DtoQn

propagationdelay An to Qn

propagationdelay LE to Qn

propagationdelay MR to Qn

propagationdelay DtoQn

propagationdelay An to Qn

propagationdelay LE to Qn

propagationdelay MR to Qn

LE pulse width HIGH or LOW

MR pulse width LOW

set-up time DtoLE, An to LE

holdtimeD to LE, An to LE

74AHC259;

74AHCT259

TEST CONDITIONS T

25 −40 to +85 −40 to +125

WAVEFORMS C

MIN. TYP. MAX. MIN. MAX. MIN. MAX.

see Figs 5 and 11 15 pF − 4.1 7.5 1.0 9.0 1.0 10.0 ns

see Figs 6 and 11 − 5.5 9.5 1.0 11.5 1.0 12.5 ns

see Figs 7 and 11 − 4.3 8.0 1.0 9.5 1.0 10.4 ns

see Figs 8 and 11 − 3.9 7.0 1.0 8.5 1.0 9.5 ns

see Figs 5 and 11 50 pF − 5.4 9.5 1.0 11.0 1.0 12.0 ns

see Figs 6 and 11 − 6.6 12.0 1.0 14.0 1.0 15.5 ns

see Figs 7 and 11 − 5.5 10.0 1.0 12.0 1.0 13.0 ns

see Figs 8 and 11 − 5.1 9.0 1.0 10.5 1.0 11.5 ns

see Figs 7 and 11 5.0 −−5.0 − 5.0 − ns

see Figs 8 and 11 5.0 −−5.0 − 5.0 − ns

see Figs 9,

4.0 −−4.0 − 4.0 − ns

10 and 11 see Figs 9 and 11 1.0 −−1.0 − 1.0 − ns

amb

(°C)

UNIT

Note

1. Typical values at V

= 5.0 V.

2000 Mar 14 12

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Philips Semiconductors Product speciﬁcation

8-bit addressable latch

AC WAVEFORMS

D input

(1)

GND

PHL

VI INPUT

REQUIREMENTS

(2)

(1)

INPUT

50% V

handbook, halfpage

Qn output

FAMILY

AHC GND to V AHCT GND to 3.0 V 1.5 V 50% V

PLH

MNA569

(2)

OUTPUT

50% V

CC CC

74AHC259;

74AHCT259

handbook, halfpage

An input

Qn output

FAMILY

AHC GND to V AHCT GND to 3.0 V 1.5 V 50% V

(1)

GND

PHL

VI INPUT

REQUIREMENTS

(2)

(1)

INPUT

50% V

OUTPUT

50% V

MNA568

PLH

(2)

CC CC

Fig.5 The data input (D) to output (Qn)

propagation delays.

handbook, full pagewidth

FAMILY

REQUIREMENTS

AHC GND to V

D input

LE input

Qn output

VI INPUT

GND

INPUT

50% V

(1)

AHCT GND to 3.0 V 1.5 V 50% V

(1)

PHL

(2)

OUTPUT

50% V

CC CC

Fig.6 The address input (An) to output (Qn)

propagation delays.

PLH

(2)

MNA570

Fig.7 The enable input (LE) to output (Qn) propagation delays, the enable input pulse width.

2000 Mar 14 13

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Philips Semiconductors Product speciﬁcation

8-bit addressable latch 74AHC259; 74AHCT259

handbook, halfpage

MR input

Qn output

FAMILY

AHC GND to V

GND

VI INPUT

REQUIREMENTS

(1)

PHL

INPUT

50% V

(2)

(1)

OUTPUT

50% V

AHCT GND to 3.0 V 1.5 V 50% V

Fig.8 The conditional reset input (MR) to output

(Qn) propagation delays.

MNA548

(2)

CC CC

An input

LE input

FAMILY

GND

VI INPUT

REQUIREMENTS

(1)

ADDRESS STABLE

(1)

INPUT

50% V

(1)

handbook, halfpage

The shaded areas indicate whenthe inputis permittedto changefor predictable output performance.

AHC GND to V AHCT GND to 3.0 V 1.5 V

Fig.9 The address set-up and hold time for

An inputs to LE input.

MNA550

handbook, full pagewidth

FAMILY

REQUIREMENTS

AHC GND to V

LE input

Qn output

VI INPUT

GND

D input

GND

(1)

INPUT

50% VCC50% V

AHCT GND to 3.0 V 1.5 V 50% V

Fig.10 The data set-up and hold time for D input to LE input.

(2)

OUTPUT

CC CC

(1)

(2)

The shaded areas indicate when the input is permitted to change for predictable output performance.

Q = DQ = D

MNA549

2000 Mar 14 14

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Philips Semiconductors Product speciﬁcation

8-bit addressable latch

handbook, full pagewidth

GENERATOR

TEST S1

PLH/tPHL

PLZ/tPZL

PHZ/tPZH

open V

GND

PULSE

Definitions for test circuit. CL= load capacitance including jig and probe capacitance (See Chapter “AC characteristics”). RT= termination resistance should be equal to the output impedance Zo of the pulse generator.

D.U.T.

1000 Ω

MNA219

open GND

74AHC259;

74AHCT259

Fig.11 Load circuitry for switching times.

2000 Mar 14 15

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Philips Semiconductors Product speciﬁcation

8-bit addressable latch

PACKAGE OUTLINES

SO16: plastic small outline package; 16 leads; body width 3.9 mm

74AHC259;

74AHCT259

SOT109-1

v M

pin 1 index

0 2.5 5 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

UNIT

inches

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

A1A2A3b

max.

0.25

1.75

0.10

0.010

0.069

0.004

1.45

1.25

0.057

0.049

0.25

0.01

0.49

0.36

0.019

0.014

0.25

0.19

0.0100

0.0075

(1)E(1) (1)

10.0

9.8

0.39

0.38

scale

eHELLpQZywv θ

4.0

1.27

3.8

0.16

0.050

0.15

w M

6.2

5.8

0.244

0.228

1.05

0.041

detail X

1.0

0.7

0.4

0.6

0.028

0.039

0.020

0.016

(A )

0.25 0.1

0.25

0.01

0.01 0.004

0.7

0.3

0.028

0.012

OUTLINE

VERSION

SOT109-1

IEC JEDEC EIAJ

076E07 MS-012

REFERENCES

2000 Mar 14 16

EUROPEAN

PROJECTION

ISSUE DATE

97-05-22 99-12-27

Page 17

Philips Semiconductors Product speciﬁcation

8-bit addressable latch

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm

74AHC259;

74AHCT259

v M

SOT403-1

pin 1 index

w M

DIMENSIONS (mm are the original dimensions)

UNIT A

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

max.

1.10

OUTLINE

VERSION

SOT403-1 MO-153

0.15

0.05

A2A

0.95

0.80

IEC JEDEC EIAJ

0.25

0.30

0.19

0 2.5 5 mm

scale

(1)E(2) (1)

0.2

5.1

4.5

0.1

REFERENCES

4.9

4.3

0.65

eHELLpQZywv θ

6.6

6.2

(A )

detail X

0.75

0.4

0.50

0.3

EUROPEAN

PROJECTION

0.13 0.10.21.0

0.40

0.06

ISSUE DATE

95-04-04 99-12-27

2000 Mar 14 17

Page 18

Philips Semiconductors Product speciﬁcation

8-bit addressable latch

SOLDERING Introduction to soldering surface mount packages

Thistext gives averybrief insighttoa complex technology. A more in-depth account of soldering ICs can be found in our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011). There is no soldering method that is ideal for all surface

mount IC packages.Wave solderingis notalways suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used.

Reﬂow soldering

Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied tothe printed-circuitboardby screenprinting,stencilling or pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method.

Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C.

Wave soldering

Conventional single wave soldering is not recommended forsurface mount devices(SMDs)or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems.

To overcome these problems the double-wave soldering method was specifically developed.

74AHC259;

74AHCT259

If wave soldering is used the following conditions must be observed for optimal results:

• Use a double-wave soldering method comprising a turbulent wavewith high upwardpressure followed bya smooth laminar wave.

• For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the printed-circuit board.

The footprint must incorporate solder thieves at the downstream end.

• Forpackages with leadsonfour sides, thefootprintmust be placedat a 45° angle to the transportdirection of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners.

During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured.

Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.

Manual soldering

Fix the component by first soldering two diagonally-opposite end leads. Use a lowvoltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C.

When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C.

2000 Mar 14 18

Page 19

Philips Semiconductors Product speciﬁcation

8-bit addressable latch

74AHC259;

74AHCT259

Suitability of surface mount IC packages for wave and reﬂow soldering methods

PACKAGE

BGA, LFBGA, SQFP, TFBGA not suitable suitable HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not suitable

(3)

PLCC LQFP, QFP, TQFP not recommended SSOP, TSSOP, VSO not recommended

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;

5. Wave soldering is onlysuitable for SSOP and TSSOPpackages with a pitch (e)equal to or larger than0.65 mm; it is

, SO, SOJ suitable suitable

temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the

(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

The package footprint must incorporate solder thieves downstream and at the side corners.

it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

WAVE REFLOW

(2)

SOLDERING METHOD

suitable

(3)(4) (5)

suitable suitable

(1)

DEFINITIONS

Data sheet status

Objective speciﬁcation This data sheet contains target or goal speciﬁcations for product development. Preliminary speciﬁcation This data sheet contains preliminary data; supplementary data may be published later. Product speciﬁcation This data sheet contains ﬁnal product speciﬁcations.

Limiting values

Limiting valuesgiven are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the speciﬁcation is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the speciﬁcation.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.

2000 Mar 14 19

Page 20

Philips Semiconductors – a w orldwide compan y

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Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 800 943 0087

Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. +381 11 3341 299, Fax.+381 11 3342 553

For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.

2000

Internet: http://www.semiconductors.philips.com

Printed in The Netherlands 613507/01/pp20 Date of release: 2000 Mar 14 Document order number: 9397 750 06821