Datasheet 74ACTQ841SPC, 74ACTQ841SCX, 74ACTQ841SC, 74ACTQ841CW Datasheet (Fairchild Semiconductor)
Page 1
March 1990
Revised November 1998
74ACTQ841 Quiet Series 10-Bit Transparent Latch with 3-STATE Outputs
© 1999 Fairchild Semiconductor Corporation DS010688.prf www.fairchildsemi.com
74ACTQ841
Quiet Series 10-Bit Transparent Latch
with 3-STATE Outputs
General Description
The ACTQ841 bus interface latch is de signed to eli minate
the extra packages required to buffer existing latches and
provide extra data width for wider address/data paths or
buses carrying parity. The 841 is a 10-bit transparent latch,
a 10-bit version of the 373. The ACTQ841 utilizes Fairchild
Quiet Series technology to guarantee quiet output switching and improved dynamic threshold pe rformance. FACT
Quiet Series features GTO output control and undershoot
corrector in addition to a spl it ground bus for superior pe rformance.
Features
■ Guaranteed simultaneous switching noise level and
dynamic threshold performance
■ Guaranteed pin-to-pin skew AC performance
■ Inputs and outputs on opposit e sides of package allow
easy interface with microprocessors
■ Improved latch-up immunity
■ Outputs source/sink 24 mA
■ Has TTL-com patible inputs
Ordering Code:
Device also available in Tape and Reel. Specify by appendin g s uf f ix let t er “X” to the ordering co de.
Logic Symbols Connection Diagram
Pin Assignment
for DIP and SOIC
Pin Descriptions
FACT, Quiet Series, FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Co rporation.
Order Number Package Number Package Description
74ACTQ841SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ACTQ841SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC, MS-100, 0.300” Wide
Pin Names Description
D
0–D9
Data Inputs
O
0–O9
3-STATE Outputs
OE
Output Enable
LE Latch Enable
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74ACTQ841
Functional Description
The ACTQ841 consists of ten D -ty pe latches with 3-STATE
outputs. The flip-flops ap pea r transparent to the data whe n
Latch Enable (LE) is HIGH. This allows asynchronous
operation, as the output transition follows the data in transition.
On the LE HIGH-to-LOW transition, the data that meets the
setup and hold time is lat ched. Data appears on the bus
when the Output Enable (O E
) is LOW. When OE is HIGH
the bus output is in the high impedance state.
Function Table
H = HIGH Voltage Level
L = LOW V oltage Level
X = Immaterial
Z = High Impedance
NC = No Change
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimat e propagation delays.
Inputs Internal Output Function
OE
LE D Q O
X X X X Z High Z
H H L L Z High Z
H H H H Z High Z
H L X NC Z Latched
L H L L L Transparent
L H H H H Transparent
L L X NC NC Latched
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74ACTQ841
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without exception, to ensure th at the system design is reliable over its power
supply, temperature, and output/in put loading variables. Fairchild does n ot
recommend operat ion of FACT circuits outside databook specifications.
DC Electrical Characteristics
Note 2: All outputs loaded; thresholds on input associated with ou t put under test.
Supply Voltage (VCC) − 0.5V to + 7.0V
DC Input Diode Current (I
IK
)
V
I
= − 0.5V − 20 mA
V
I
= VCC + 0.5V + 20 mA
DC Input Voltage (V
I
) − 0.5V to VCC + 0.5V
DC Output Diode Current (I
OK
)
V
O
= − 0.5V − 20 mA
V
O
= VCC + 0.5V + 20 mA
DC Output Voltage (V
O
) − 0.5V to VCC + 0.5V
DC Output Source
or Sink Current (I
O
) ± 50 mA
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
) ± 50 mA
Storage Temperature (T
STG
) − 65°C to + 150°C
DC Latch-Up Source
or Sink Current ± 300 mA
Junction Temperature (T
J
)
PDIP 140°C
Supply Voltage (V
CC
) 4.5V to 5.5V
Input Voltage (V
I
)0V to V
CC
Output Voltage (VO)0V to V
CC
Operating Temperature (TA) − 40°C to + 85°C
Minimum Input Edge Rate ∆V/∆t 125 mV/ns
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V
Symbol Parameter
V
CC
TA = +25°CT
A
= − 40°C to +85°C
Units Conditions
(V) Typ Guaranteed Limits
V
IH
Minimum High Level 4.5 1.5 2.0 2.0 V V
OUT
= 0.1V
Input Voltage 5.5 1.5 2.0 2.0 or VCC − 0.1V
V
IL
Maximum Low Level 4.5 1.5 0.8 0.8 V V
OUT
= 0.1V
Input Voltage 5.5 1.5 0.8 0.8 or VCC − 0.1V
V
OH
Minimum High Level 4.5 4.49 4.4 4.4 V I
OUT
= − 50 µA
Output Voltage 5.5 5.49 5.4 5.4
VIN = VIL or V
IH
4.5 3.86 3.76 V IOH = − 24 mA
5.5 4.86 4.76 IOH = − 24 mA (Note 2)
V
OL
Maximum Low Level 4.5 0.001 0.1 0.1 V I
OUT
= 50 µA
Output Voltage 5.5 0.001 0.1 0.1
VIN = VIL or V
IH
4.5 0.36 0.44 V IOL = − 24 mA
5.5 0.36 0.44 IOL = − 24 mA (Note 2)
I
IN
Maximum Input 5.5 ± 0.1 ± 1.0 µAVI = VCC, GND
Leakage Current
I
OZ
Maximum 3- STATE 5.5 ± 0.5 ± 5.0 µAVI = VIL, V
IH
Leakage Current VO = VCC, GND
I
CCT
Maximum ICC/Input 5.5 0.6 1.5 mA VI = VCC − 2.1V
I
OLD
Minimum Dynamic 5.5 75 mA V
OLD
= 1.65V Max
I
OHD
Output Current (Note 3) 5.5 −75 mA V
OHD
= 3.85V Min
I
CC
Maximum Quiescent 5.5 8.0 80.0 µAVIN = VCC or GND
Supply Current
V
OLP
Quiet Output 5.0 1.1 1.5 V Figure 1, Figure 2
Maximum Dynamic V
OL
(Note 4)(Note 5)
V
OLV
Quiet Output 5.0 −0.6 −1.2 V Figure 1, Figure 2
Minimum Dynamic V
OL
(Note 4)(Note 5)
V
IHD
Minimum High Level 5.0 1.9 2.2 V (Note 4)(Note 6)
Dynamic Input Voltage
V
ILD
Maximum Low Level 5.0 1.2 0.8 V (Note 4)(Note 6)
Dynamic Input Voltage
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74ACTQ841
DC Electrical Characteristics (Continued)
Note 3: Maximum test duration 2.0 ms, one output loaded at a tim e.
Note 4: PDIP package.
Note 5: Max number of outputs defined as (n) . Data inputs are driven 0 V t o 3V. One output @ GND.
Note 6: Max number of data inputs (n) switching. (n − 1) inputs switching 0V to 3V (ACTQ). Input-under-tes t switching:
3V to threshold (V
ILD
), 0V to threshold (V
IHD
), f = 1 MHz.
AC Electrical Charac teristics
Note 7: Voltage Range 5.0 is 5.0V ± 0.5V.
Note 8: Skew is defined as t he absolute value o f th e difference between the actual propagation delay for any two ou tp ut s w it hin the same packaged device.
The specificati on applies to any out puts switching i n the sa me directi on, either HI GH to LOW (t
OSHL
) or LOW to HIGH (t
OSLH
). Parameter guaranteed by
design. Not tested.
AC Operating Requirements
Note 9: Voltage Range 5.0 is 5.0V ±0.5V.
Capacitance
V
CC
TA = +25°CT
A
= −40°C to +85°C
Symbol Parameter (V)
CL = 50 pF CL = 50 pF
Units
(Note 7) Min Typ Max Min Max
t
PLH
Propagation Delay 5.0 2.5 7.0 9.5 2.0 10.0 ns
t
PHL
Dn to O
n
t
PLH
Propagation Delay 5.0 2.5 7.0 9.5 2.0 10.0 ns
t
PHL
LE to O
n
t
PZH
Output Enable Time 5.0 2.5 8.5 11.0 2.0 12.0 ns
t
PZL
OE to O
n
t
PHZ
Output Disable Time 5.0 1.0 6.0 9.0 1.0 9.5 ns
t
PLZ
OE to O
n
t
OSLH
Output to Output 5.0 0.5 1.0 1.0 ns
t
OSHL
Skew Dn to On (Note 8)
V
CC
TA = + 25 TA = − 40°C to + 85°C
Symbol Parameter (V)
CL = 50 pF °CC
L
= 50 pF
Units
(Note 9) Typ Guaranteed Minimum
t
S
Setup Time, HIGH or LOW 5.0 3.0 3.0 ns
Dn to LE
t
H
Hold Time, HIGH or LOW 5.0 1.5 1.5 ns
Dn to LE
t
W
LE Pulse Width, HIGH 5.0 4.0 4.0 ns
Symbol Parameter Typ Units Conditions
C
IN
Input Capacitance 4.5 pF VCC = OPEN
C
PD
Power Dissipation Capacitance 85.0 pF VCC = 5.0V
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74ACTQ841
FACT Noise Characteristics
The setup of a noise characteristics measurement is critical
to the accuracy and repeatability of the tests. The following
is a brief description of the setup used to measure the
noise characteristics of FACT.
Equipment:
Hewlett Packard Model 8180A Word Generator
PC-163A Test Fixture
Tektronics Model 7854 Oscilloscope
Procedure:
1. Verify Test Fixture Loading: Standard Load 50 pF,
500Ω.
2. Deskew the HFS generator so th at no two channels
have greater than 150 ps skew between them. This
requires that the oscilloscope be des kewe d first. It is
important to deskew the HFS generator channels
before testing. This will ensu re that the outputs switch
simultaneously.
3. Ter m ina te al l inp uts an d ou tputs to ensure proper loading of the outputs and that the input levels are at the
correct voltage.
4. Set the HFS generator to toggle a ll but one output a t a
frequency of 1 MHz. Greate r frequencies will increase
DUT heating and effect the results of the measurement.
5. Set the HFS generator inp ut levels at 0V LOW and 3V
HIGH for ACT devices and 0V LOW and 5 V HIGH for
AC devices. Verify levels with an oscilloscope.
Note A: V
OHV
and V
OLP
are measured with respect to ground reference.
Note B: Input pulses have the following characteristics: f = 1 MHz, t
r
= 3ns,
t
f
= 3 ns, skew < 150 ps.
FIGURE 1. Quiet Output Noise Voltage Waveforms
V
OLP/VOLV
and V
OHP/VOHV
:
• Determine the quiet output pin that demonstrates the
greatest noise levels. The worst case pin will usually be
the furthest from the ground pin. Mon i tor the ou tpu t voltages using a 50Ω coaxial cable plugged into a stand ard
SMB type connector on the test fixture. Do not use an
active FET probe.
• Measure V
OLP
and V
OLV
on the quiet output du ring the
worst case transition for active and enable. Measure
V
OHP
and V
OHV
on the quiet output during the worst
case active and enable transition.
• Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements.
V
ILD
and V
IHD
:
• Monitor one of the switching outputs using a 50 Ω coaxial
cable plugged into a standard SMB type connec tor on
the test fixture. Do not use an active FET probe.
• First increase the input LOW voltage level, V
IL
, until the
output begins to oscilla te or steps out of a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds V
IL
limits, or on output HIGH levels that
exceed V
IH
limits. The input LOW voltage level at which
oscillation occurs is defined as V
ILD
.
• Next decrease the input HIGH voltage level, V
IH
, until
the output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds V
IL
limits, or on output HIGH levels that
exceed V
IH
limits. The input HIGH voltage level at which
oscillation occurs is defined as V
IHD
.
• Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements.
FIGURE 2. Simultaneous Switching Test Circuit
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74ACTQ841
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
Package Number M24B
Page 7
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchi ld reserves the right at any time without notice to change said circuitry and specifications.
74ACTQ841 Quiet Series 10-Bit Transparent Latch with 3-STATE Outputs
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or system s a re devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injur y to the
user.
2. A critical compon ent in any com ponent of a li fe support
device or system whose failure to p erform can be r easonably expected to cause the failure of the life suppor t
device or system, or to affect its safety or effectiveness.
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300” Wide
Package Number N24C
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