Datasheet 74ACTQ827SPC, 74ACTQ827SCX, 74ACTQ827SC, 74ACTQ827CW Datasheet (Fairchild Semiconductor)
Page 1
March 1990
Revised December 1998
74ACTQ827 Quiet Series 10-Bit Buffer/Li ne Driver with 3-STATE Outputs
© 1999 Fairchild Semiconductor Corporation DS010687.prf www.fairchildsemi.com
74ACTQ827
Quiet Series 10-Bit Buffer/Line Driver
with 3-STATE Outputs
General Description
The ACTQ827 10-bit bus buffer provides high per for man ce
bus interface buffering for wide data/address paths or
buses carrying parity. The 10-bit buffers have NOR output
enables for maximum control flexibility. The ACTQ827 utilizes Fairchild Quiet Series technology to guarantee quiet
output switching and improved dynam ic threshold performance. FACT Quiet Series features G TO output control
and undershoot correct or in addition t o a split ground bus
for superior performance.
Features
■ Guaranteed simultaneous switching noise level and
dynamic threshold performance
■ Guaranteed pin-to-pin skew AC performance
■ Inputs and outputs on opposit e sides of package allow
easy interface with microprocessors
■ Improved latch-up immunity
■ Outputs source/sink 24 mA
■ Functionally and pin-compatible to AMD’s AM29827
■ Has TTL-com patible inputs
Ordering Code:
Device also available in Tape and Reel. Specify by appendin g s uf f ix let t er “X” to the ordering co de.
Logic Symbols
IEEE/IEC
Connection Diagram
Pin Assignment
for DIP and SOIC
Pin Descriptions
FACT, Quiet Series, FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Co rporation.
Order Number Package Number Package Description
74ACTQ827SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ACTQ827SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300” Wide
Pin Names Description
OE
1
, OE
2
Output Enable
D
0–D9
Data Inputs
O
0–O9
Data Outputs
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74ACTQ827
Functional Description
The ACTQ827 line driver is designed to be employed as
memory address driver, clock driver and bus-oriented
transmitter/receiver. The devices have 3-STATE outputs
controlled by the Output Enable (OE
) pins. When the OE is
LOW, the device is transparent. When OE
is HIGH, the
device is in 3-STATE mode.
Function Table
H = HIGH Voltage Level
L = LOW Voltage Level
Z = HIGH Impedance
X = Immaterial
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate p ropagation delays.
Inputs Outputs Function
OE
D
n
O
n
L H H Transparent
L L L Transparent
H X Z High Z
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74ACTQ827
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power
supply, temperature, and output/in put loading variables. Fairchild does n ot
recommend operat ion of FACT circuits outside databook specifications.
DC Electrical Characteristic
Supply Voltage (VCC) −0.5V to +7.0V
DC Input Diode Current (I
IK
)
V
I
= −0.5V −20 mA
V
I
= VCC + 0.5V +20 mA
DC Input Voltage (V
I
) −0.5V to VCC + 0.5V
DC Output Diode Current (I
OK
)
V
O
= −0.5V −20 mA
V
O
= VCC + 0.5V +20 mA
DC Output Voltage (V
O
) −0.5V to VCC + 0.5V
DC Output Source
or Sink Current (I
O
) ± 50 mA
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
) ± 50 mA
Storage Temperature (T
STG
) −65°C to +150°C
DC Latch-Up Source
or Sink Current ± 300 mA
Junction Temperature (T
J
)
PDIP 140°C
Supply Voltage (V
CC
) 4.5V to 5.5V
Input Voltage (V
I
)0V to V
CC
Output Voltage (VO)0V to V
CC
Operating Temperature (TA) −40°C to +85°C
Minimum Input Edge Rate ∆V/∆t 125 mV/ns
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V
Symbol Parameter
V
CC
TA = +25°CT
A
= −40°C to +85°C
Units Conditions
(V) Typ Guaranteed Limits
V
IH
Minimum HIGH Level 4.5 1.5 2.0 2.0 V V
OUT
= 0.1V
Input Voltage 5.5 1.5 2.0 2.0 or VCC − 0.1V
V
IL
Maximum LOW Level 4.5 1.5 0.8 0.8 V V
OUT
= 0.1V
Input Voltage 5.5 1.5 0.8 0.8 or VCC − 0.1V
V
OH
Minimum HIGH Level 4.5 4.49 4.4 4.4 V I
OUT
= −50 µA
Output Voltage 5.5 5.49 5.4 5.4
VIN = VIL or V
IH
4.5 3.86 3.76 V IOH = −24 mA
5.5 4.86 4.76 IOH = −24 mA (Note 2)
V
OL
Maximum LOW Level 4.5 0.001 0.1 0.1 V I
OUT
= 50 µA
Output Voltage 5.5 0.001 0.1 0.1
VIN = VIL or V
IH
4.5 0.36 0.44 V IOL = 24 mA
5.5 0.36 0.44 IOL = 24 mA (Note 2)
I
IN
Maximum Input 5.5 ±0.1 ±1.0 µAVI = VCC, GND
Leakage Current
I
OZ
Maximum 3-STATE 5.5 ±0.5 ±5.0 µAVI = VIL, V
IH
Current VO = VCC, GND
I
CCT
Maximum ICC/Input 5.5 0.6 1.5 mA VI = VCC − 2.1V
I
OLD
Minimum Dynamic 5.5 75 mA V
OLD
= 1.65V Max
I
OHD
Output Current (Note 3) 5.5 −75 mA V
OHD
= 3.85V Min
I
CC
Maximum Quiescent 5.5 8.0 80.0 µAVIN = V
CC
Supply Current or GND
V
OLP
Quiet Output 5.0 1.1 1.6V V Figure 1, Figure 2
Maximum Dynamic V
OL
(Note 4)(Note 5)
V
OLV
Quiet Output 5.0 −0.6 −1.3 V Figure 1, Figure 2
Minimum Dynamic V
OL
(Note 4)(Note 5)
V
IHD
Minimum HIGH Level 5.0 1.9 2.0 V (Note 4)(Note 6)
Dynamic Input Voltage
V
ILD
Maximum LOW Level 5.0 1.2 0.8 V (Note 4)(Note 6)
Dynamic Input Voltage
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74ACTQ827
DC Electrical Characteristic (Continued)
Note 2: All outputs loaded; thresholds on input associated w it h output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: DIP package.
Note 5: Max number of outputs defined as (n). Data inputs are dr iven 0 V t o 3V. One output @ GN D.
Note 6: Max number of data inputs (n−1) inputs switching 0V to 3V (ACTQ). Input-under-test switching:
3V to threshold (V
ILD
), 0V to threshold. (V
IHD
), f = 1 MHz.
AC Electrical Charac teristics
Note 7: Voltage Range 5.0 is 5.0V ±0.5V.
Note 8: Skew is defined as t he absolute value o f th e difference between t he actual propagation delay for any two outp ut s w it hin the same packaged device.
The specificati on applies to any out puts switching i n the sa me directi on, either HI GH to LOW (t
OSHL
) or LOW to HIGH (t
OSLH
). Parameter guaranteed by
design. Not tested.
Capacitance
V
CC
TA = +25°CT
A
= −40°C to +85°C
Symbol Parameter (V)
CL = 50 pF CL = 50 pF
Units
(Note 7) Min Typ Max Min Max
t
PHL
Propagation Delay 5.0 2.5 5.6 8.0 2.5 9.0 ns
t
PLH
Data to Output
t
PZL tPZH
Output Enable Time 5.0 3.0 7.1 10.0 3.0 11.0 ns
t
PHZ tPLZ
Output Disable Time 5.0 1.0 5.8 8.0 1.0 8.5 ns
t
OSHL
Output to Output 5.0 0.5 1.5 1.5 ns
t
OSLH
Skew (Note 8)
Data to Output
Symbol Parameter Typ Units Conditions
C
IN
Input Capacitance 4.5 pF VCC = OPEN
C
PD
Power Dissipation Capacitance 82 pF VCC = 5.0V
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74ACTQ827
FACT Noise Characteristics
The setup of a noise characteristics measurement is critical
to the accuracy and repeatability of the tests. The following
is a brief description of the setup used to measure the
noise characteristics of FACT.
Equipment:
Hewlett Packard Model 8180A Word Generator
PC-163A Test Fixture
Tektronics Model 7854 Oscilloscope
Procedure:
1. Verify Test Fixture Loading: Standard Load 50 pF,
500Ω.
2. Deskew the HFS generator so th at no two channels
have greater than 150 ps skew between them. This
requires that the oscilloscope be des kewed first. It is
important to deskew the HFS generator channels
before testing. This will ensu re that the outputs switch
simultaneously.
3. Terminate all inputs and ou tpu ts to en sur e pr ope r l oa ding of the outputs and that the input levels are at the
correct voltage.
4. Set the HFS generator to toggle a ll but one output a t a
frequency of 1 MHz. Greater frequencies will increase
DUT heating and effect the results of the measurement.
5. Set the word generato r inpu t levels at 0V L OW and 3V
HIGH for ACT devices and 0V LOW and 5 V HIGH for
AC devices. Verify levels with an oscilloscope.
Note 9: V
OHV
and V
OLP
are measured with re s pec t t o ground reference.
Note 10: Input pulses have the following characteristics: f =1 MHz,
t
r
= 3 ns, tf= 3 ns, skew < 150ps.
FIGURE 1. Quiet Output Noise Voltage Waveforms
V
OLP/VOLV
and V
OHP/VOHV
:
• Determine the quiet output pin that demonstrates the
greatest noise levels. The worst case pin will usually be
the furthest from the ground pin. Mon i tor the ou tpu t voltages using a 50Ω coaxial cable plugged into a stand ard
SMB type connector on the test fixture. Do not use an
active FET probe.
• Measure V
OLP
and V
OLV
on the quiet output du ring the
worst case transition for active and enable. Measure
V
OHP
and V
OHV
on the quiet output during the worst
case active and enable transition.
• Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements.
V
ILD
and V
IHD
:
• Monitor one of the switching outputs usin g a 50Ω coaxial
cable plugged into a standard SMB type connec tor on
the test fixture. Do not use an active FET probe.
• First increase the input LOW voltage level, V
IL
, until the
output begins to os cillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds V
IL
limits, or on output HIGH levels that
exceed V
IH
limits. The input LOW voltage level at which
oscillation occurs is defined as V
ILD
.
• Next decrease the input HIGH voltage level, V
IH
, until
the output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds V
IL
limits, or on output HIGH levels that
exceed V
IH
limits. The input HIGH voltage level at which
oscillation occurs is defined as V
IHD
.
• Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements.
FIGURE 2. Simultaneous Switching Test Circuit
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74ACTQ827
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
Package Number M24B
Page 7
Fairchild does not assume any responsibility for use of any circuitry descri bed, no circuit patent licenses are impli ed and Fairchild reser ves the right at any time without notice to change said circuitry and specifications.
74ACTQ827 Quiet Series 10-Bit Buffer/Li ne Driver with 3-STATE Outputs
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or system s a re devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injur y to the
user.
2. A critical compon ent in any com ponent of a li fe support
device or system whose failure to p erform can be r easonably expected to cause the failure of the life suppor t
device or system, or to affect its safety or effectiveness.
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300” Wide
Package Number N24C
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