Datasheet 74ACTQ574SJX, 74ACTQ574SJ, 74ACTQ574SCX, 74ACTQ574SC, 74ACTQ574PC Datasheet (Fairchild Semiconductor)
...Page 1
© 1999 Fairchild Semiconductor Corporation DS010634 www.fairchildsemi.com
January 1990
Revised November 1999
74ACQ574 • 74ACTQ574 Quiet Series Octal D-Type Flip-Flop with 3-STATE Outputs
74ACQ574 • 74ACTQ574
Quiet Series Octal D-Type Flip-Flop
with 3-STATE Outputs
General Description
The ACQ/ACTQ57 4 is a high-speed, low-po wer octal Dtype flip-flop with a buffered Commo n Clock (CP) and a
buffered common Output Enable (OE
). The information
presented to the D inputs is stor ed in the flip-flops on the
LOW-to-HIGH clock (CP) transition.
ACQ/ACTQ574 utilize s FACT Quiet Ser ies technology to
guarantee quiet output switching and improve dynamic
threshold performance . FACT Quiet Series feat ure s GTO
output control and undershoot corrector in addition to a
split ground bus for superior performance.
The ACQ/ACTQ574 is functionally identical to the
ACTQ374 bu t with different pin-out.
Features
■ ICC and IOZ reduced by 5 0%
■ Guaranteed simultaneous switching noise level and
dynamic threshold performan ce
■ Guarante ed pin-to-pin skew AC performance
■ Inputs and outputs on opposite sides of the package
allowing easy interface with microprocessors
■ Functionally identical to the ACQ/ACTQ374
■ 3-STATE outputs drive bus lines or buffer memory
address registers
■ Outputs source/sink 24 mA
■ Faster prop delays than the standard AC/ACT574
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix “X” to the ordering code.
Connection Diagram Pin Descriptions
FACT, Qui et Series , FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation.
Order Number Package Number Package Description
74ACQ574SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ACQ574SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACQ574PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
74ACTQ574SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ACTQ574SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACTQ574PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Pin Names Description
D
0–D7
Data Inputs
CP Clock Pulse Input
OE
3-STATE Output Enable Input
O
0–O7
3-STATE Outputs
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74ACQ574 • 74ACTQ574
Logic Symbols
IEEE/IEC
Functional Description
The ACQ/ACTQ574 consists of eight edge-trigger ed flipflops with individual D- type inputs and 3-STATE true outputs. The buffered clock a nd buffered Output Enable a re
common to all flip-flops. The eight flip-flops will sto re the
state of their individ ual D-type inputs that mee t the setup
and hold time requirements on the LOW-to-HIGH Clock
(CP) transition. With the Output Enable (OE
) LOW, the
contents of the eight flip-flops are avai lable at th e outputs.
When OE
is HIGH, the out puts go to the high impedance
state. Operation of the OE
input does not affect the state of
the flip-flops.
Function Table
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
= LOW-to-HIGH Transition
NC = No Change
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Inputs Internal Outputs
Function
OE CP D Q O
N
H H L NC Z Hold
HHH NC Z Hold
H
LL ZLoad
H
HH ZLoad
L
L L L Data Available
L
H H H Data Available
L H L NC NC No Change in Data
L H H NC NC No Change in Data
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74ACQ574 • 74ACTQ574
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
Note 1: Absolute max imum ratings are those values beyond which da m age
to the device may occu r. The databook spe cificatio ns shou ld be met, wit hout exception, to ensure that the system de sign is relia ble over its p ower
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside datab ook s pecifications.
DC Electrical Characteristics for ACQ
Supply Voltage (VCC) −0.5V to +7.0V
DC Input Diode Current (I
IK
)
V
I
= −0.5V −20 mA
V
I
= VCC + 0.5V +20 mA
DC Input Voltage (V
I
) −0.5V to VCC + 0.5V
DC Output Diode Current (I
OK
)
V
O
= −0.5V −20 mA
V
O
= VCC + 0.5V +20 mA
DC Output Voltage (V
O
) −0.5V to VCC + 0.5V
DC Output S ource
or Sink Current (I
O
) ±50 mA
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
) ±50 mA
Storage Temperature (T
STG
) −65°C to +150°C
DC Latch-Up Source or
Sink Current ±300 mA
Junction Temperature (T
J
)
PDIP 140°C
Supply Voltage (V
CC
)
ACQ 2.0V to 6.0V
ACTQ 4.5V to 5.5V
Input Voltage (V
I
)0V to V
CC
Output Voltage (VO)0V to V
CC
Operating Temperature (TA) −40°C to +85°C
Minimum Input Edge Rate ∆V/∆t
ACQ Devices
V
IN
from 30% to 70% of V
CC
VCC @ 3.0V, 4.5V, 5.5V 125 mV/ns
Minimum Input Edge Rate ∆V/∆t
ACTQ Devices
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V 125 mV/ns
Symbol Parameter
V
CC
TA = +25°CT
A
= −40°C to +85°C
Units Conditions
(V) Typ Guaranteed Limits
V
IH
Minimum HIGH Level 3.0 1.5 2.1 2.1 V
OUT
= 0.1V
Input Voltage 4.5 2.25 3.15 3.15 V or VCC − 0.1V
5.5 2.75 3.85 3.85
V
IL
Maximum LOW Level 3.0 1.5 0.9 0.9 V
OUT
= 0.1V
Input Voltage 4.5 2.25 1.35 1.35 V or VCC − 0.1V
5.5 2.75 1.65 1.65
V
OH
Minimum HIGH Level 3.0 2.99 2.9 2.9
Output Voltage 4.5 4.49 4.4 4.4 V I
OUT
= −50 µA
5.5 5.49 5.4 5.4
VIN = VIL or V
IH
3.0 2.56 2.46 IOH = −12 mA
4.5 3.86 3.76 V I
OH
= −24 mA
5.5 4.86 4.76 I
OH
= −24 mA (Note 2)
V
OL
Maximum LOW Level 3.0 0.002 0.1 0.1
Output Voltage 4.5 0.001 0.1 0.1 V I
OUT
= 50 µA
5.5 0.001 0.1 0.1
VIN = VIL or V
IH
3.0 0.36 0.44 IOL = 12 mA
4.5 0.36 0.44 V IOL = 24 mA
5.5 0.36 0.44 IOL = 24 mA (Note 2)
I
IN
Maximum Input
5.5 ±0.1 ±1.0 µAVI = VCC, GND
(Note 4) Leakage Current
I
OLD
Minimum Dynamic 5.5 75 mA V
OLD
= 1.65V Max
I
OHD
Output Current (Note 3) 5.5 −75 mA V
OHD
= 3.85V Min
I
CC
Maximum Quiescent
5.5 4.0 40.0 µA
VIN = V
CC
(Note 4) Supply Current or GND
I
OZ
Maximum 3-STATE VI (OE) = VIL, V
IH
Leakage Current 5.5 ±0.25 ±2.5 µAVI = VCC, GND
VO = VCC, GND
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74ACQ574 • 74ACTQ574
DC Electrical Characteristics for ACQ (Continued)
Note 2: All outputs loaded; thresholds on input assoc iat ed with output under tes t.
Note 3: Maximum test duratio n 2. 0 ms, one output loaded at a time.
Note 4: I
IN
and ICC @ 3.0V are guaranteed to be less than or equa l to th e respective limit @ 5.5V VCC.
Note 5: DIP package .
Note 6: Max number of output s d ef ined as (n). Data inputs ar e driven 0V to 5V. One output @ GND.
Note 7: Maximum number of data inputs (n) switching. (n−1) inputs switching 0V to 5V (ACQ). Input-under-test switching:
5V to threshold (V
ILD
), 0V to threshold (V
IHD
). f = 1 MHz.
DC Electrical Characteristics for ACTQ
Note 8: All outputs loaded; thresholds on input assoc iat ed with output under tes t.
Note 9: Maximum test duratio n 2. 0 ms, one output loaded at a time.
Note 10: DIP package.
Note 11: Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output @ GND.
Symbol Parameter
V
CC
TA = +25°CT
A
= −40°C to +85°C
Units Conditions
(V) Typ Guaranteed Limits
V
OLP
Quiet Output
5.0 1.1 1.5 V
Figure 1, Figure 2
Maximum Dynamic V
OL
(Note 5)(Note 6)
V
OLV
Quiet Output
5.0 −0.6 −1.2 V
Figure 1, Figure 2
Minimum Dynamic V
OL
(Note 5)(Note 6)
V
IHD
Minimum HIGH Level
5.0 3.1 3.5 V (Note 5)(Note 7)
Dynamic Input Voltage
V
ILD
Maximum LOW Level
5.0 1.9 1.5 V (Note 5)(Note 7)
Dynamic Input Voltage
Symbol Parameter
V
CC
TA = +25°CT
A
= −40°C to +85°C
Units Conditions
(V) Typ Guaranteed Limits
V
IH
Minimum HIGH Level 4.5 1.5 2.0 2.0
V
V
OUT
= 0.1V
Input Voltage 5.5 1.5 2.0 2.0 or V
CC
− 0.1V
V
IL
Maximum LOW Level 4.5 1.5 0.8 0.8
V
V
OUT
= 0.1V
Input Voltage 5.5 1.5 0.8 0.8 or VCC − 0.1V
V
OH
Minimum HIGH Level 4.5 4.49 4.4 4.4
VI
OUT
= −50 µA
Output Voltage 5.5 5.49 5.4 5.4
VIN = VIL or V
IH
4.5 3.85 3.76 V IOH= −24 mA
5.5 4.86 4.76 I
OH
= −24 mA (Note 8)
V
OL
Maximum LOW Level 4.5 0.001 0.1 0.1
VI
OUT
= 50 µA
Output Voltage 5.5 0.001 0.1 0.1
VIN = VIL or V
IH
4.5 0.36 0.44 V IOL = 24 mA
5.5 0.36 0.44 I
OL
= 24 mA (Note 8)
I
IN
Maximum Input Leakage Current 5.5 ±0.1 ±1.0 µAVI = VCC, GND
I
OZ
Maximum 3-STATE
5.5 ±0.25 ±2.5 µA
VI = VIL, V
IH
Leakage Current VO = VCC, GND
I
CCT
Maximum ICC/Input 5.5 0.6 1.5 mA VI = VCC − 2.1V
I
OLD
Minimum Dynamic 5.5 75 mA V
OLD
= 1.65V Max
I
OHD
Output Current (Note 9) 5.5 −75 mA V
OHD
= 3.85V Min
I
CC
Maximum Quiescent
5.5 4.0 40.0 µA
VIN = V
CC
Supply Current or GND
V
OLP
Quiet Output
5.0 1.1 1.5 V
Figure 1, Figure 2
Maximum Dynamic V
OL
(Note 10)(Note 11)
V
OLV
Quiet Output
5.0 −0.6 −1.2 V
Figure 1, Figure 2
Minimum Dynamic V
OL
(Note 10)(Note 11)
V
IHD
Minimum HIGH Level
5.0 1.9 2.2 V (Note 10)(Note 12)
Dynamic Input Voltage
V
ILD
Maximum LOW Level
5.0 1.2 0.8 V (Note 10)(Note 12)
Dynamic Input Voltage
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74ACQ574 • 74ACTQ574
DC Electrical Characteristics for ACTQ (Continued)
Note 12: Max number of data inputs (n) switching. (n−1) inputs switching 0V to 3V (ACTQ). In put-under-test switch ing:
3V to threshold (V
ILD
), 0V to threshold (V
IHD
), f = 1 MHz.
AC Electrical Characteristics for ACQ
Note 13: Voltage Ran ge 5.0 is 5.0V ± 0.5V
Voltage Range 3.3 is 3.3V ± 0.3V
Note 14: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the sam e d evice. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
). Parameter guaranteed by des ign.
AC Operating Requirements for ACQ
Note 15: Voltage Ran ge 5.0 is 5.0V ± 0.5V
Voltage Range 3.3 is 3.3V ± 0.3V
AC Electrical Characteristics for ACTQ
Note 16: Voltage Ran ge 5.0 is 5.0V ± 0.5V.
Note 17: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the sam e d evice. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
). Parameter guaranteed by des ign.
V
CC
TA = +25°CT
A
= −40°C to +85°C
Symbol Parameter (V)
C
L
= 50 pF CL = 50 pF
Units
(Note 13) Min Typ Max Min Max
f
MAX
Maximum Clock 3.3 75 70
MHz
Frequency 5.0 90 85
t
PLH
Propagation Delay 3.3 3.0 9.5 13.0 3.0 13.5
ns
t
PHL
CP to O
n
5.0 2.0 6.5 8.5 2.0 9.0
t
PZH
Output Enable Time 3.3 3.0 9.5 13.0 3.0 13.5
ns
t
PZL
5.0 2.0 6.5 8.5 2.0 9.0
t
PHZ
Output Disable Time 3.3 1.0 9.5 14.5 1.0 15.0
ns
t
PLZ
5.0 1.0 8.0 9.5 1.0 10.0
t
OSHL
Output to Output Skew (Note 14) 3.3 1.0 1.5 1.5
ns
t
OSLH
CP to O
n
5.0 0.5 1.0 1.0
V
CC
TA = +25°CT
A
= −40°C to +85°C
Symbol Parameter (V)
C
L
= 50 pF CL = 50 pF
Units
(Note 15) Typ Guaranteed Minimum
t
S
Setup Time, HIGH or LOW 3.3 0 3.0 3.0
ns
D
n
to CP 5.0 0 3.0 3.0
t
H
Hold Time, HIGH or LOW 3.3 0 1.5 1.5
ns
D
n
to CP 5.0 0 1.5 1.5
t
W
CP Pulse Width, 3.3 2.0 4.0 4.0
ns
HIGH or LOW 5.0 2.0 4.0 4.0
V
CC
TA = +25°CT
A
= −40°C to +85°C
Symbol Parameter (V)
CL = 50 pF CL = 50 pF
Units
(Note 16) Min Typ Max Min Max
f
MAX
Maximum Clock Frequency 5.0 85 80 MHz
t
PLH
Propagation Delay
5.02.07.09.02.09.5ns
t
PHL
CP to O
n
t
PZH
Output Enable
5.02.07.09.02.09.5ns
t
PZL
Time
t
PHZ
Output Disable
5.0 1.0 8.0 10.0 1.0 10.5 ns
t
PLZ
Time
t
OSHL
Output to Output Skew (Note 17)
5.0 0.5 1.0 1.0 ns
t
OSLH
CP to O
n
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74ACQ574 • 74ACTQ574
AC Operating Requirements for ACTQ
Note 18: Voltage Range 5.0 is 5.0V ± 0.5V
Capacitance
V
CC
TA = +25°CT
A
= −40°C to +85°C
Symbol Parameter (V)
C
L
= 50 pF CL = 50 pF
Units
(Note 18) Typ Guaranteed Minimum
t
S
Setup Time, HIGH or LOW
5.0 0 3.0 3.0 ns
D
n
to CP
t
H
Hold Time, HIGH or LOW
5.0 0 1.5 1.5 ns
D
n
to CP
t
W
CP Pulse Width,
5.0 2.0 4.0 4.0 ns
HIGH or LOW
Symbol Parameter Typ Units Conditions
C
IN
Input Capacitance 4.5 pF VCC = OPEN
C
PD
Power Dissipation Capacitance 40.0 pF VCC = 5.0V
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74ACQ574 • 74ACTQ574
FACT Noise Characteristics
The setup of a noise characteristics measurement is critical
to the accuracy and repeatability of the tests. The following
is a brief description of the setup used to measure the
noise characteristics of FACT.
Equipment:
Hewlett Packard Model 8180A Word Generator
PC-163A Test Fixture
Tektronics Model 7854 Oscilloscope
Procedure:
1. Verify Test Fixture Loading: Standard Load 50 pF,
500Ω.
2. Deskew the HFS generator so that no two channels
have greater than 150 ps skew between them. This
requires that the oscilloscope be deskewed first. It is
important to deskew the HFS generator channels
before testing. This will ensure that the outputs switch
simultaneously.
3. Terminate all inputs and outputs to ensure proper load-
ing of the outputs and that the input levels are at the
correct voltage.
4. Set the HFS generator to togg le all bu t one ou tput at a
frequency of 1 MHz. Greater frequencies will increase
DUT heating and effect the results of the measurement.
5. Set the HFS genera tor in put l evels at 0V LO W a nd 3V
HIGH for ACT devices and 0V LOW and 5V HIGH for
AC devices. Verify levels with an oscilloscope.
Note 19: V
OHV
and V
OLP
are measured with respect to ground reference.
Note 20: Input pulses have the following characteristics: f = 1 MHz,
t
r
= 3ns, tf = 3ns, skew < 150 ps.
FIGURE 1. Quiet Output Noise Voltage Waveforms
V
OLP/VOLV
and V
OHP/VOHV
:
• Determine the quiet output pin that demonstrates the
greatest noise levels. The worst case pin will us ually be
the furthest from th e g rou nd pin . Monitor the output vol tages using a 50Ω coaxial ca ble plug ged i nto a stand ard
SMB type connector on the test fixture. Do not use an
active FET probe.
• Measure V
OLP
and V
OLV
on the quiet output du ring the
worst case for active and enable transition. Measure
V
OHP
and V
OHV
on the quiet output during the worst
case active and enable transition.
• Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements.
V
ILD
and V
IHD
:
• Monitor one of the switching outputs using a 50Ω coaxial
cable plugged into a st andard SMB type connector on
the test fixture. Do not use an active FET probe.
• First increase the input LOW voltage level, V
IL
, until the
output begins to oscillate or steps o ut a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds V
IL
limits, or on output HIGH levels that
exceed V
IH
limits. The input LOW voltage level at which
oscillation occurs is defined as V
ILD
.
• Next decrease the input HIGH voltage level, V
IH
, until
the output begins to osci llate or steps o ut a m in o f 2 ns .
Oscillation is defined as noise on the output LOW level
that exceeds V
IL
limits, or on output HIGH levels that
exceed V
IH
limits. The input HIGH voltage level at which
oscillation occurs is defined as V
IHD
.
• Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements.
FIGURE 2. Simultaneous Switching Test Circuit
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74ACQ574 • 74ACTQ574
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Bod y
Package Number M20B
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74ACQ574 • 74ACTQ574
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
Page 10
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74ACQ574 • 74ACTQ574 Quiet Series Octal D-Type Flip-Flop with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitr y described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant inju ry to the
user.
2. A critical component in any compon ent of a lif e support
device or system whose failure t o perform can be reasonably expected to ca use the failure of the life supp ort
device or system, or to affect its safety or effectiveness.
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