Datasheet 74ACTQ573SJX, 74ACTQ573SJ, 74ACTQ573SCX, 74ACTQ573SC, 74ACTQ573QSCX Datasheet (Fairchild Semiconductor)

© 1999 Fairchild Semiconductor Corporation DS010633 www.fairchildsemi.com

January 1990
Revised November 1999

74ACQ573 • 74ACTQ573 Quiet Series Octal Latch with 3-STATE Outputs

74ACQ573 • 74ACTQ573
Quiet Series Octal Latch with 3-STAT E Outputs

General Description

The ACQ/ACTQ573 is a high-speed oct al latch with buff­ered common Latch Enable (LE) and buffered common
Output Enable (OE

) inputs. The A CQ/ACTQ573 is func­tionally identical to the ACQ/ACT Q373 but with inputs and
outputs on opposite sides of th e pa ckag e. T he AC Q/ ACTQ
utilizes Fairchild’s Quiet Series technology to guarant ee
quiet output switching and improved dynamic threshold
performance. FACT Quiet Series features GTO output
control and undershoot corrector in addition to a split
ground bus for superior performance.

Features

■ ICC and IOZ reduced by 5 0%

■ Guaranteed simultaneous switching noise level and

dynamic threshold performan ce

■ Guarante ed pin-to-pin skew AC per formance

■ Improved latch-up immunity

■ Inputs and outputs on opposit e sides of package allow

easy interface with microprocessors

■ Outputs source/sink 24 mA

Ordering Code:

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbols

IEEE/IEC

Connection Diagram

Pin Descriptions

FACT, Qui et Series , FACT Quiet Series, an d GTO are trademarks of Fairchild Semiconductor Corporation

Order Number Package Number Package Description

74ACQ573SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ACQ573SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74ACQ573MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

74ACQ573PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
74ACTQ573SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ACTQ573SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACTQ573QSC MQA20 20-Lead Quarter Size Outline Package (QSOP), JEDEC MO -13 7, 0.15 0” Wide
74ACTQ573PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Pin Names Description

D

0–D7

Data Inputs
LE Latch Enable Input
OE

3-STATE Output Enable Input
O

0–O7

3-STATE Latch Outputs

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74ACQ573 • 74ACTQ573

Functional Description

The ACQ/ACTQ573 contains eight D-type latches with 3­STATE output buffers. When the Latch Enable (LE) input is
HIGH, data on the D

n

inputs enters the latches. In this con-

dition the latches are transparent, i.e., a la tch output will
change state each time its D-type input changes. When LE
is LOW the latche s store the inf ormation that was prese nt
on the D-type inpu ts at setup time prece ding th e HIGH-to­LOW transition of LE . The 3-STATE buffers are controlled
by the Output Enable (OE

) input. When OE is LOW, the

buffers are enabled. W hen OE

is HIGH the buffers are i n
the high impedance mode but this doe s not interfere with
entering new data into the latches.

Tr uth Table

H = HIGH V oltage
L = LOW Voltage
Z = High Impedance
X = Immaterial
O

0

= Previous O0 before HIGH-to-LOW transition of Latch Enable

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

Inputs Outputs

OE LE D O

n

LHH H
LHL L
LLX O

0

HXX Z

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74ACQ573 • 74ACTQ573

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: Absolute max imum ratings are those values beyon d w hich damage

to the device may occu r. The databook spe cificatio ns shou ld be met, wit h­out exception, to ensure that the system de sign is relia ble over its p ower
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specific at ions.

DC Electrical Characteristics for ACQ

Supply Voltage (VCC) −0.5V to +7.0V
DC Input Diode Current (I

IK

)

V

I

= −0.5V −20 mA

V

I

= VCC + 0.5V +20 mA

DC Input Voltage (V

I

) −0.5V to VCC + 0.5V

DC Output Diode Current (I

OK

)

V

O

= −0.5V −20 mA

V

O

= VCC + 0.5V +20 mA

DC Output Voltage (V

O

) −0.5V to VCC + 0.5V

DC Output S ource

or Sink Current (I

O

) ±50 mA

DC V

CC

or Ground Current

per Output Pin (I

CC

or I

GND

) ±50 mA

Storage Temperature (T

STG

) −65°C to +150°C

DC Latchup Source

or Sink Current ±300 mA

Junction Temperature (T

J

PDIP 140°C

Supply Voltage (V

CC

)
ACQ 2.0V to 6.0V
ACTQ 4.5V to 5.5V

Input Voltage (V

I

)0V to V

CC

Output Voltage (VO)0V to V

CC

Operating Temperature (TA) −40°C to +85°C
Minimum Input Edge Rate ∆V/∆t

ACQ Devices
V

IN

from 30% to 70% of V

CC

VCC @ 3.0V, 4.5V, 5.5V 125 mV/ns

Minimum Input Edge Rate ∆V/∆t

ACTQ Devices
V

IN

from 0.8V to 2.0V

V

CC

@ 4.5V, 5.5V 125 mV/ns

Symbol Parameter

V

CC

TA = +25°CTA = −40°C to +85°C

Units Conditions

(V) Typ Guaranteed Limits

V

IH

Minimum HIGH Level 3.0 1.5 2.1 2.1 V

OUT

= 0.1V

Input Voltage 4.5 2.25 3.15 3.15 V or VCC − 0.1V

5.5 2.75 3.85 3.85

V

IL

Maximum LOW Level 3.0 1.5 0.9 0.9 V

OUT

= 0.1V

Input Voltage 4.5 2.25 1.35 1.35 V or VCC − 0.1V

5.5 2.75 1.65 1.65

V

OH

Minimum HIGH Level 3.0 2.99 2.9 2.9
Output Voltage 4.5 4.49 4.4 4.4 V I

OUT

= −50 µA

5.55.495.4 5.4
VIN = VIL or V

IH

3.0 2.56 2.46 IOH = −12 mA

4.5 3.86 3.76 V I

OH

= −24 mA

5.5 4.86 4.76 I

OH

= −24 mA (Note 2)

V

OL

Maximum LOW Level 3.0 0.002 0.1 0.1
Output Voltage 4.5 0.001 0.1 0.1 V I

OUT

= 50 µA

5.5 0.001 0.1 0.1
VIN = VIL or V

IH

3.0 0.36 0.44 IOL = 12 mA

4.5 0.36 0.44 V IOL = 24 mA

5.5 0.36 0.44 IOL = 24 mA (Note 2)

IIN (Note 4) Maximum Input Leakage Current 5.5 ± 0.1 ± 1.0 µAVI = VCC, GND
I

OLD

Minimum Dynamic 5.5 75 mA V

OLD

= 1.65 V

Max

I

OHD

Output Current (Note 3) 5.5 −75 mA V

OHD

= 3.85 V

Min

ICC (Note 4) Maximum Quiescent Supply Current 5.5 4.0 40.0 µAVIN = VCC or GND
I

OZ

Maximum 3- STATE VI (OE) = VIL, V

IH

Leakage Current 5.5 ±0.25 ±2.5 µAVI = VCC, GND

VO = VCC, GND

V

OLP

Quiet Output

5.0 1.1 1.5 V

Figure 1, Figure 2

Maximum Dynamic V

OL

(Note 5)(Note 6)

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74ACQ573 • 74ACTQ573

DC Electrical Characteristics for ACQ (Continued)

Note 2: All outputs loaded; thresholds on input assoc iat ed with output under tes t.
Note 3: Maximum test duratio n 2. 0 ms, one output loaded at a time.
Note 4: I

IN

and ICC @ 3.0V are guaranteed to be less than or equa l to th e respective limit @ 5.5V VCC.

Note 5: Plastic DIP package.
Note 6: Max number of outputs defined as (n). Data Inputs are driven 0V to 5V. One output @ GND.
Note 7: Max number of Data Inputs (n) switching. (n − 1) Inputs switching 0V to 5V (ACQ). Input-under-test switching: 5V to threshold (V

ILD

),

0V to threshold (V

IHD

), f = 1 MHz.

DC Electrical Characteristics for ACTQ

Note 8: All outputs loaded; thresholds on input assoc iat ed with output under tes t.
Note 9: Maximum test duratio n 2. 0 ms, one output loaded at a time.
Note 10: Plastic DI P package.
Note 11: Max number of outputs defined as (n). Data Inputs are driven 0V to 3V. One output @ GND.
Note 12: Max number of data inp ut s (n) s w it c hing. (n − 1) inputs switching 0V to 3V (ACTQ). Input-under-test switching: 3V to threshold (V

ILD

),

0V to threshold (V

IHD

), f =1 MHz.

Symbol Parameter

V

CC

TA = +25°CTA = −40°C to +85°C

Units Conditions

(V) Typ Guaranteed Limits

V

OLV

Quiet Output

5.0 −0.6 −1.2 V

Figure 1, Figure 2

Minimum Dynamic V

OL

(Note 5)(Note 6)

V

IHD

Minimum HIGH Level

5.0 3.1 3.5 V (Note 5)(Note 7)

Dynamic Input Voltage

V

ILD

Maximum LOW Level

5.0 1.9 1.5 V (Note 5)(Note 7)

Dynamic Input Voltage

Symbol Parameter

V

CC

TA = +25°CTA = −40°C to +85°C

Units Conditions

(V) Typ Guaranteed Limits

V

IH

Minimum HIGH Level 4.5 1.5 2.0 2.0

V

V

OUT

= 0.1V

Input Voltage 5.5 1.5 2.0 2.0 or VCC − 0.1V

V

IL

Maximum LOW Level 4.5 1.5 0.8 0.8

V

V

OUT

= 0.1V

Input Voltage 5.5 1.5 0.8 0.8 or V

CC

− 0.1V

V

OH

Minimum HIGH Level 4.5 4.49 4.4 4.4

VI

OUT

= −50 µA

Output Voltage 5.5 5.49 5.4 5.4

VIN = VIL or V

IH

4.5 3.86 3.76 V IOH = −24 mA

5.5 4.86 4.76 I

OH

= −24 mA (Note 8)

V

OL

Maximum LOW Level 4.5 0.001 0.1 0.1

VI

OUT

= 50 µA

Output Voltage 5.5 0.001 0.1 0.1

VIN = VIL or V

IH

4.5 0.36 0.44 V IOL = 24 mA

5.5 0.36 0.44 IOL = 24 mA (Note 8)

I

IN

Maximum Input

5.5 ±0.1 ±1.0 µAV

I

= VCC, GND

Leakage Current

I

OZ

Maximum 3-STATE

5.5 ±0.25 ±2.5 µA

VI = VIL, V

IH

Leakage Current VO = VCC, GND

I

CCT

Maximum ICC/Input 5.5 0.6 1.5 mA VI = VCC − 2.1V

I

OLD

Minimum Dynamic 5.5 75 mA V

OLD

= 1.65V Max

I

OHD

Output Current (Note 9) 5.5 −75 mA V

OHD

= 3.85V Min

I

CC

Maximum Quiescent Supply Current 5.5 4.0 40.0 µAVIN = VCC or GND

V

OLP

Quiet Output

5.0 1.1 1.5 V

Figure 1, Figure 2

Maximum Dynamic V

OL

(Note 10)(Note 11)

V

OLV

Quiet Output

5.0 −0.6 −1.2 V

Figure 1, Figure 2

Minimum Dynamic V

OL

(Note 10)(Note 11)

V

IHD

Minimum HIGH Level

5.0 1.9 2.2 V (Note 10)(Note 12)

Dynamic Input Voltage

V

ILD

Maximum LOW Level

5.0 1.2 0.8 V (Note 10)(Note 12)

Dynamic Input Voltage

5 www.fairchildsemi.com

74ACQ573 • 74ACTQ573

AC Electrical Characteristics for ACQ

Note 13: Voltage Ran ge 5.0 is 5.0V ± 0.5V

Voltage Range 3.3 is 3.3V ± 0.3V

Note 14: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the sam e d evice. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t

OSHL

) or LOW-to-HIGH (t

OSLH

). Parameter guarantee d by design.

AC Operating Requirements for ACQ

Note 15: Voltage Range 5.0 is 5.0V ± 0.5V

Voltage Range 3.3 is 3.3V ± 0.3V

AC Electrical Characteristics for ACTQ

Note 16: Voltage Ran ge 5.0 is 5.0V ± 0.5V
Note 17: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the sam e d evice. The

specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t

OSHL

) or LOW-to-HIGH (t

OSLH

). Parameter guarantee d by design.

V

CC

TA = +25°CT

A

= −40°C to +85°C

Symbol Parameter (V)

C

L

= 50 pF CL = 50 pF

Units

(Note 13) Min Typ Max Min Max

t

PHL

Propagation Delay 3.3 2.5 8.5 10.5 2.5 11.0

ns

t

PLH

Dn to O

n

5.0 1.5 5.5 7.0 1.5 7.5

t

PLH

Propagation Delay 3 .3 2.5 8.5 12.0 2.5 12.5

ns

t

PHL

LE to O

n

5.0 2.0 6.0 8.0 2.0 8.5

t

PZL

Output Enable Time 3.3 2.5 8.5 13.0 2.5 13.5

ns

t

PZH

5.0 1.5 6.0 8.5 1.5 9.0

t

PHZ

Output Disable Time 3.3 1 .0 9.0 14.5 1.0 15.0

ns

t

PLZ

5.0 1.0 6.0 9.5 1.0 10.0

t

OSHL

Output to Output Skew (Note 14) 3.3 1.0 1.5 1.5

ns

t

OSLH

Dn to O

n

5.0 0.5 1.0 1.0

V

CC

TA = +25°C TA = −40°C to +85°C

Symbol Parameter (V)

CL = 50 pF CL = 50 pF

Units

(Note 15) Typ Guaranteed Minimum

t

S

Setup Time, HIGH or LOW 3.3 0 3.0 3.0

ns

Dn to LE 5.0 0 3.0 3.0

t

H

Hold Time, HIGH or LOW 3.3 0 1.5 1.5

ns

Dn to LE 5.0 0 1.5 1.5

t

W

LE Pulse Width, HIGH 3.3 2.0 4.0 4.0

ns

5.0 2.0 4.0 4.0

V

CC

TA = +25°CT

A

= −40°C to +85°C

Symbol Parameter (V)

C

L

= 50 pF CL = 50 pF

Units

(Note 16) Min Typ Max Min Max

t

PHL

Propagation Delay

5.02.06.57.52.08.0ns

t

PLH

Dnto O

n

t

PLH

Propagation Delay

5.02.57.08.52.59.0ns

t

PHL

LE to O

n

t

PZL

, t

PZH

Output Enable Time 5.0 2.0 7.0 9.0 2.0 9.5 ns

t

PHZ

, t

PLZ

Output Disable Time 5.0 1.0 8.0 10.0 1.0 10.5 ns

t

OSHL

Output to Output Skew (Note 17)

5.0 0.5 1.0 1.0 ns

t

OSLH

Dn to O

n

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74ACQ573 • 74ACTQ573

AC Operating Requirements for ACTQ

Note 18: Voltage Range 5.0 is 5.0V ± 0.5V

Capacitance

V

CC

TA = +25°CT

A

= −40°C to +85°C

Symbol Parameter (V)

C

L

= 50 pF CL = 50 pF

Units

(Note 18) Typ Guaranteed Minimum

t

S

Setup Time, HIGH or LOW

5.0 0 3.0 3.0 ns

D

n

to LE

t

H

Hold Time, HIGH or LOW

5.0 0 1.5 1.5 ns

D

n

to LE

t

W

LE Pulse Width, HIGH 5.0 2.0 4.0 4.0 ns

Symbol Parameter Typ Units Conditions

C

IN

Input Capacitance 4.5 pF VCC = OPEN

C

PD

Power Dissipation Capacitance 42.0 pF VCC = 5.0V

7 www.fairchildsemi.com

74ACQ573 • 74ACTQ573

FACT Noise Characteristics

The setup of a noise characteristics measurement is critical
to the accuracy and repeatability of the tests. The following
is a brief description of the setup used to measure the
noise characteristics of FACT.

Equipment:

Hewlett Packard Model 8180A Word Generator
PC-163A Test Fixture
Tektronics Model 7854 Oscilloscope

Procedure:

1. Verify Test Fixture Loading: Standard Load 50 pF,
500Ω.

2. Deskew the HFS ge nerator so that no two channels
have greater than 150 ps skew between them. This
requires that the oscilloscope be deskewed first. It is
important to deskew the HFS generator channels
before testing. This will ensure that the outputs switch
simultaneously.

3. Terminate all inputs and outputs to ensure proper load­ing of the outputs and that the input levels are the cor­rect voltage.

4. Set the HFS ge nerato r to togg le all bu t one ou tput at a
frequency of 1 MHz. Greater frequencies will increase
DUT heating and affect the results of the measure­ment.

5. Set the HF S g enera tor in put l evels at 0V LO W a nd 3V
HIGH for ACT devices and 0V LOW and 5V HIGH for
AC devices. Verify levels with an oscilloscope.

Note 19: V

OHV

and V

OLP

are measured with respect to ground reference.

Note 20: Input pulses have the following characteristics: f = 1MHz,
t

r

= 3ns, tf= 3ns, skew< 150 ps.

FIGURE 1. Quiet Output Noise Voltage Waveforms

V

OLP/VOLV

and V

OHP/VOHV

:

• Determine the quiet output pin that demonstrates the
greatest noise levels. The worst case pin will us ually be
the furthest from th e g rou nd pin . Monitor the output vol t­ages using a 50Ω coaxial ca ble plug ged i nto a stand ard
SMB type connector on the test fixture. Do not use an
active FET probe.

• Measure V

OLP

and V

OLV

on the quiet output du ring the

worst case transition for active and enable. Measure
V

OHP

and V

OHV

on the quiet output during the worst

case active and enable transition.

• Verify that the GND reference recorded o n the oscillo­scope has not drifted to ensure the accuracy and repeat­ability of the measurements.

V

ILD

and V

IHD

:

• Monitor one of the switching outputs using a 50Ω coaxial
cable plugged into a st andard SMB type connector on
the test fixture. Do not use an active FET probe.

• First increase the input LOW voltage level, V

IL

, until the

output begins to oscillate or steps o ut a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds V

IL

limits, or on output HIGH levels that

exceed V

IH

limits. The input LOW voltage level at which

oscillation occurs is defined as V

ILD

.

• Next decrease the input HIGH voltage level, V

IH

, until

the output begins to osci llate or steps o ut a m in o f 2 ns .
Oscillation is defined as noise on the output LOW level
that exceeds V

IL

limits, or on output HIGH levels that

exceed V

IH

limits. The input HIGH voltage level at which

oscillation occurs is defined as V

IHD

.

• Verify that the GND reference recorded o n the oscillo­scope has not drifted to ensure the accuracy and repeat­ability of the measurements.

FIGURE 2. Simultaneous Switching Test Circuit

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74ACQ573 • 74ACTQ573

Physical Dimensions inches (millimeters) unless otherwise noted

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body

Package Number M20B

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74ACQ573 • 74ACTQ573

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M20D

www.fairchildsemi.com 10

74ACQ573 • 74ACTQ573

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150” Wide

Package Number MQA20

11 www.fairchildsemi.com

74ACQ573 • 74ACTQ573

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Thin Shrink Sm all Ou tline Pa ck age (TS SO P), JE DE C MO-153, 4.4mm Wide

Package Number MTC20

www.fairchildsemi.com 12

74ACQ573 • 74ACTQ573 Quiet Series Octal Latch with 3-STATE Outputs

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Package Number N20A

Fairchild does not assume any responsibility for use of any circuitr y described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r systems a re devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea­sonably expected to result in a significant inju ry to the
user.

2. A critical compon ent i n any compon ent of a lif e supp ort
device or system whose failure t o perform can be rea­sonably expected to ca use the failure of the life supp ort
device or system, or to affect its safety or effectiveness.

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