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January 1990
Revised December 1998
74ACTQ563
Quiet Series Octal Latch with 3-STATE Outputs
74ACTQ563 Quiet Series Octal Latch wit h 3-STATE Outputs
General Description
The ACTQ563 is a high speed octal latch with buffered
common Latch Enable (LE) an d buffered common Output
Enable (OE
to the ACTQ573, but with inverted outp uts. The ACTQ563
utilizes Fairchild FACT Quiet Series technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series features GTO
output control and undershoot corrector in addition to a
split ground bus for superior performance.
) inputs. The ACTQ563 is function ally identical
Features
■ ICC and IOZ reduced by 50%
■ Guaranteed simultaneous switching noise level and
dynamic threshold performance
■ Guaranteed pin-to-pin skew AC performance
■ Improved latch-up immunity
■ Inputs and outputs on opposi te sides of package allow
easy interface with microprocessors
■ Outputs source/sink 24 mA
■ Faster prop delays than standard ACT563
■ Functionally iden tical to the ACTQ573 but w ith inverted
outputs
Ordering Code:
Order Number Package Number Package Description
74ACTQ563PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appendin g s uf f ix let t er “X” to the ordering co de.
Logic Symbols
IEEE/IEC
Connection Diagram
Pin Assignment for DIP
Pin Descriptions
Pin Names Description
D
0–D7
LE Latch Enable Input
OE
O
0–O7
FACT, Quiet Series, FACT Quiet Series and GTO are trademark s of Fairchild Semiconductor Co rporation.
© 1999 Fairchild Semiconductor Corporation DS010631.prf www.fairchildsemi.com
Data Inputs
3-STATE Output Enable Input
3-STATE Latch Outputs
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Functional Description
The ACTQ563 contains eig ht D-type lat ches with 3-STATE
complementar y o utp uts. Wh en the Latc h E nable (L E ) inp ut
is HIGH, data on the D
condition the latches are transparent, i.e., a latch output will
74ACTQ563
change state each time its D input changes. When LE is
LOW the latches store the information that was present on
inputs enters the latches. In this
n
Function Table
Inputs Internal Outputs Function
LE D Q O
OE
H X X X Z High-Z
H H L H Z High-Z
H H H L Z High-Z
H L X NC Z Latched
L H L H H Transparent
L H H L L Transparent
H = HIGH Voltage Level
L = LOW Voltage Lev el
X = Immaterial
Z = High Impedance
NC = No Change
L L X NC NC Latched
Logic Diagram
the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE buffers are controlled by the
Output Enable (OE) input. When OE is LOW, the buffers
are in the bi-state m od e. When OE
in the high impedance mode but that does not interfere with
entering new data into the latches.
is HIGH the buffers are
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate p ropagation delays.
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Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) −0.5V to +7.0V
DC Input Diode Current (I
= −0.5V −20 mA
V
I
= VCC + 0.5V +20 mA
V
I
DC Input Voltage (V
DC Output Diode Current (I
= −0.5V −20 mA
V
O
= VCC + 0.5V +20 mA
V
O
DC Output Voltage (V
DC Output Source
or Sink Current (I
or Ground Current
DC V
CC
per Output Pin (I
Storage Temperature (T
DC Latchup Source
)
IK
) −0.5V to VCC + 0.5V
I
O
CC
)
OK
) −0.5V to VCC + 0.5V
O
) ± 50 mA
or I
) ± 50 mA
GND
) −65°C to +150°C
STG
Junction Temperature (T
PDIP 140°C
Recommended Operating
Conditions
Supply Voltage (V
Input Voltage (V
Output Voltage (VO)0V to V
Operating Temperature (TA) −40°C to +85°C
Minimum Input Edge Rate ∆V/∆t 125 mV/ns
from 0.8V to 2.0V
V
IN
@ 4.5V, 5.5V
V
CC
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power
supply, temperature, and output/in put loading variables. Fairchild does n ot
recommend operat ion of FACT circuits outside databoo k specifications.
)
J
) 4.5V to 5.5V
CC
)0V to V
I
or Sink Current ± 300 mA
DC Electrical Characteristics
V
Symbol Parameter
V
Minimum HIGH Level 4.5 1.5 2.0 2.0 V V
IH
Input Voltage 5.5 1.5 2.0 2.0 or VCC − 0.1V
V
Maximum LOW Level 4.5 1.5 0.8 0.8 V V
IL
Input Voltage 5.5 1.5 0.8 0.8 or VCC − 0.1V
V
Minimum HIGH Level 4.5 4.49 4.4 4.4 V I
OH
Output Voltage 5.5 5.49 5.4 5.4
V
Maximum LOW Level 4.5 0.001 0.1 0.1 I
OL
Output Voltage 5.5 0.001 0.1 0.1
I
Maximum Input Leakage Current 5.5 ± 0.1 ± 1.0 µAVI = VCC, GND
IN
I
Maximum 3-STATE 5.5 ± 0.25 ± 2.5 µAVI = VIL, V
OZ
Leakage Current VO = VCC, GND
I
Maximum ICC/Input 5.5 0.6 1.5 mA VI = VCC − 2.1V
CCT
I
Minimum Dynamic 5.5 75 mA V
OLD
I
Output Current (Note 3) 5.5 −75 mA V
OHD
I
Maximum Quiescent Supply Current 5.5 4.0 40.0 µAVIN = VCC or GND
CC
V
Quiet Output 5.0 1.1 1.5 V Figure 1, Figure 2
OLP
Maximum Dynamic V
V
Quiet Output 5.0 −0.6 −1.2 V Figure 1, Figure 2
OLV
Minimum Dynamic V
V
Minimum HIGH Level
IHD
Dynamic Input Voltage
V
Maximum LOW Level
ILD
Dynamic Input Voltage
Note 2: All outputs loaded; thresholds on input associated with ou t put under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: DIP package.
Note 5: Max number of ou t puts defined as (n). Da ta inputs are driven 0V to 3V. One output @ GND.
OL
OL
CC
(V) Typ Guaranteed Limits
4.5 3.86 3.76 V IOH = −24 mA
5.5 4.86 4.76 IOH = − 24 mA (Note 2)
4.5 0.36 0.44 V IOL = 24 mA
5.5 0.36 0.44 IOL = 24 mA (Note 2)
5.0 1.9 2.2 V (Note 4)(Note 6)
5.0 1.2 0.8 V (Note 4)(Note 6)
TA = +25°CTA = −40°C to +85°C
Units Conditions
= 0.1V
OUT
= 0.1V
OUT
= − 50 µA
OUT
VIN = VIL or V
= 50 µA
OUT
VIN = VIL or V
IH
= 1.65V Max
OLD
= 3.85V Min
OHD
(Note 4)(Note 5)
(Note 4)(Note 5)
74ACTQ563
CC
CC
IH
IH
3 www.fairchildsemi.com
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DC Electrical Characteristics (Continued)
Note 6: Max number of data inputs (n) switching. (n–1) inputs switching 0V to 3 V. Input-under-test switching; 3V to threshold (V
f = 1 MHz.
74ACTQ563
), 0V to threshold (V
ILD
),
IHD
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AC Electrical Characteristics
TA = +25°CT
Symbol Parameter
V
CC
CL = 50 pF CL = 50 pF
(Note 7) Min Typ Max Min Max
t
PHL
t
PLH
t
PLH
t
PHL
t
PZL
t
PZH
t
PHZ
t
PLZ
t
OSHL
t
OSLH
Note 7: Voltage Range 5.0 is 5.0V ±0.5V and 3.3 is 3.3V ± 0.3V.
Note 8: Skew is defined as the absolute value of the differen c e between the act ual propagation delay for any two separate outputs of the same d evice. The
specification applies t o any outputs switching in the sam e direction, either HIGH to LOW (t
Propagation Delay 3.3 2.5 8.5 11.5 2.5 12.0 ns
Dn to O
n
5.0 1.5 5.5 7.5 1.5 8.0
Propagation Delay 3.3 2.5 8.5 13.0 2.5 13.5 ns
LE to O
n
5.0 2.0 6.0 8.5 2.0 9.0
Output Enable Time 3.3 2.5 8.5 13.0 2.5 13.5 ns
5.0 1.5 6.0 8.5 1.5 9.0
Output Disable Time 3.3 1.0 9.0 14.5 1.0 15.0 ns
5.0 1.0 6.5 9.5 1.0 10.0
Output to Output Skew (Note 8) 3.3 1.0 1.5 1.5 ns
Dn to O
n
5.0 0.5 1.0 1.0
) or LOW to HIGH (t
OSHL
= −40°C to +85°C
A
). Parameter guaranteed by des ign.
OSLH
Units
AC Operating Requirements
Symbol Parameter (V)
t
S
Setup Time, HIGH or LOW 3.3 0 3.0 3.0 ns
Dn to LE 5.0 0 3.0 3.0
t
H
Hold Time, HIGH or LOW 3.3 0 1.5 1.5 ns
Dn to LE 5.0 0 1.5 1.5
t
W
Note 9: Voltage Range 5.0 is 5.0V ±0.5V and 3.3V is 3.3 ± 0.3V.
LE Pulse Width, HIGH 3.3 2.0 4.0 4.0 ns
V
CC
(Note 9) Typ Guaranteed Minimum
5.0 2.0 4.0 4.0
TA = +25°CT
= −40°C to +85°C
A
CL = 50 pF CL = 50 pF
Units
74ACTQ563
Capacitance
Symbol Parameter Typ Units Conditions
C
IN
C
PD
Input Capacitance 4.5 pF VCC = OPEN
Power Dissipation Capacitance 42 pF VCC = 5.0V
5 www.fairchildsemi.com
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FACT Noise Characteristics
The setup of a noise characteristics measurement is critical
to the accuracy and repeatability of the tests. The following
is a brief description of the setup used to measure the
noise characteristics of FACT.
74ACTQ563
Equipment:
Hewlett Packard Model 8180A Word Generator
PC-163A Test Fixture
Tektronics Model 7854 Oscilloscope
Procedure:
1. Verify Test Fixture Loading: Standard Load 50 pF,
500Ω.
2. Deskew the HFS generator so that no two channels
have greater than 150 ps skew between them. This
requires that the oscilloscope be deskewed first. It is
important to deskew the HFS generator channels
before testing. This will ensure that the outputs switch
simultaneously.
3. Terminate all i npu ts an d ou tput s to en sur e pro pe r load ing of the outputs and that the input levels are at the
correct voltage.
4. Set the HFS generato r to togg le all but one o utput a t a
frequency of 1 MHz. Greate r frequencies will increa se
DUT heating and effect the results of the measurement.
V
OLP/VOLV
and V
OHP/VOHV
:
• Determine the quiet output pin that demonstrates the
greatest noise levels. The worst case pin will usually be
the furthest from the ground pin. Monitor the output voltages using a 50Ω c oaxial cable plugge d into a standa rd
SMB type connector on t he test fixture. Do not use an
active FET probe.
• Measure V
OLP
and V
on the quiet output during the
OLV
worst case transition for active and enable. Measure
and V
V
OHP
on the quiet output during the worst
OHV
case active and enable transition.
• Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements.
and V
V
ILD
IHD
:
• Monitor one of the switching outputs using a 50Ω coaxial
cable plugged into a standard SMB type connect or on
the test fixture. Do not use an active FET probe.
• First increase the input LOW voltage level, V
output begins to oscillate or steps out a min of 2 ns.
, until the
IL
Oscillation is defined as noise on the output LOW level
that exceeds V
exceed V
oscillation occurs is defined as V
• Next decrease the input HIGH voltage level, V
limits, or on output HIGH levels that
IL
limits. The input LOW voltage level at which
IH
ILD
.
, until
IH
the output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds V
exceed V
oscillation occurs is defined as V
limits, or on output HIGH levels that
IL
limits. The input HIGH voltage level at which
IH
IHD
.
• Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements.
V
and V
OHV
Input pulses have the following characteristics:
f = 1 MHz, t
are measured with re s pec t to ground reference.
OLP
= 3 ns, tf = 3 ns, skew < 150 ps.
r
FIGURE 1. Quiet Output Noise Voltage Waveforms
5. Set the HFS genera tor inp ut levels at 0V LOW and 3V
HIGH for ACT devices and 0V LOW and 5V HIGH for
AC devices. Verify levels with a n oscilloscope.
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FIGURE 2. Simultaneous Switching Test Circuit
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Physical Dimensions inches (millimeters) unless otherwise noted
74ACTQ563 Quiet Series Octal Latch wit h 3-STATE Outputs
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or system s a re devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the label in g, can be re asonably expected to result i n a significant injur y to the
user.
Package Number N20A
2. A critical componen t in a ny compon ent of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reser ves the right at any time without notice to change said circuitry and specifications.
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