Datasheet 74ACTQ541SCX, 74ACTQ541SC, 74ACTQ541PC, 74ACTQ541MTCX, 74ACTQ541MTC Datasheet (Fairchild Semiconductor)

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March 1993 Revised November 1999

74ACTQ541 Quiet Series Octal Buffer/Line Driver with 3-STATE Outputs

74ACTQ541 Quiet Series Octa l Buff e r/Line Driver

with 3-STATE Outputs

General Description

The 74ACTQ541 is an octal buffer/line driver designed to be employed as memory and address drivers, clock drivers and bus oriented transmitter/receivers.

This device is similar in function to the 74ACTQ244 while providing flow-through architecture (inputs on opposite side from outputs). This pinout ar rangement makes this de vice especially useful as an output port for microprocessors, allowing ease of layout and greater PC board density.

The 74ACTQ541 utilizes FACT Quiet Series technology to guarantee quiet outp ut switchi ng and im proved dyna mic threshold performance . FACT Quiet Series feat ure s GTO output control and und ershoot corre ctor in additio n to split ground bus for superior performance.

Features

■ ICC and IOZ reduced by 5 0%

■ Guaranteed simultaneous switching noise level and

dynamic threshold performan ce

■ Guarante ed pin-to-pin skew AC per formance

■ Inputs and outputs on opposite sides of package for

easy board layout

■ Non-inverting 3-STATE outputs

■ Guarante ed 4 kV minimum ESD immunity

■ TTL compatible inputs

■ Outputs source/sink 24 mA

Ordering Code:

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the order code.

Logic Symbol

IEEE/IEC

Pin Descriptions

Connection Diagram

Truth T able

H = HIGH Voltage Level X = Immaterial L = LOW Voltage Level Z = High Impedance

FACT, FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation.

Order Number Package Number Package Description

74ACTQ541SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74ACTQ541MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74ACTQ541PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Pin Name Pin Description

– OE23-STATE Output Enable (Active-LOW)

–I

Inputs

– O

Outputs

Inputs

Outputs

LLHH HXXZ XHXZ LLLL

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74ACTQ541

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: Absolute maximum ratings are those values beyond which damage

to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and ou tput/inp ut loadi ng varia bles. Fairchild does no t recommend operat ion of FACT circuits outside da t abook specifications.

DC Electrical Characteristics

Note 2: All outputs loaded; thresholds on input assoc iat ed with output under tes t. Note 3: Maximum test duratio n 2. 0 ms, one output loaded at a time. Note 4: Plastic DIP package. Note 5: Max number of output s d ef ined as (n). Data inputs ar e driven 0V to 3V. One output @ GND. Note 6: Max number of Data Inputs (n) switching. (n–1) Inputs switching 0V to 5V (ACQ). Input-under-test switching: 5V to threshold (V

ILD

0V to threshold (V

IHD

), f = 1 MHz.

Supply Voltage (VCC) −0.5V to +7.0V DC Input Diode Current (I

)

= −0.5V −20 mA

= VCC + 0.5V +20 mA

DC Input Voltage (V

) −0.5V to VCC + 0.5V

DC Output Diode Current (I

)

= −0.5V −20 mA

= VCC + 0.5V +20 mA

DC Output Voltage (V

) −0.5V to VCC + 0.5V

DC Output Source or Sink Current (I

) ±50 mA

DC V

or Ground Current

per Output Pin (I

or I

GND

) ±50 mA

Storage Temperature (T

STG

) −65°C to +150°C DC Latch-up Source or Sink Current ± 300 mA Junction Temperature (T

)140°C

Supply Voltage V

4.5V to 5.5V

Input Voltage (V

) 0V to V

Output Voltage (VO) 0V to V

Operating Temperature (TA) −40°C to +85°C Minimum Input Edge Rate ∆V/∆t

from 0.8V to 2.0V

@ 4.5V, 5.5V 125 mV/ns

Symbol Parameter

TA = +25°CT

= −40°C to +85°C

Units Conditions

(V) Typ Guaranteed Limits

Minimum HIGH Level 4.5 1.5 2.0 2.0

OUT

= 0.1V

Input Voltage 5.5 1.5 2.0 2.0 or VCC − 0.1V

Maximum LOW Level 4.5 1.5 0.8 0.8

OUT

= 0.1V

Input Voltage 5.5 1.5 0.8 0.8 or VCC − 0.1V

Minimum HIGH Level 3.0 2.99 2.9 2.9

OUT

= −50 µA

Output Voltage 4.5 4.49 4.4 4.4

4.5 3.86 3.76 V

VIN = VIL or VIH (Note 2) IOH = −24 mA

−24 mA

5.5 4.86 4.76

Maximum LOW Level 3.0 0.002 0.1 0.1

OUT

= 50 µA

Output Voltage 4.5 0.001 0.1 0.1

4.5 0.36 0.44 V

VIN = VIL or VIH (Note 2) I

= 24 mA

24 mA

5.5 0.36 0.44

Maximum Input Leakage Current 5.5 ± 0.1 ± 1.0 µAVI = VCC, GND

Maximum 3-STATE

5.5 ±0.25 ±2.5 µA

VI = VIL, V

Leakage Current VO = VCC, GND

CCT

Maximum ICC/Input 5.5 0.6 1.5 mA VI = VCC − 2.1V

OLD

Minimum Dynamic 5.5 75 mA V

OLD

= 1.65V Max

OHD

Output Current (Note 3) 5.5 −75 mA V

OHD

= 3.85V Min

Maximum Quiescent Supply Current

5.5 4.0 40.0 µAVIN = VCC or GND

OLP

Quiet Output

5.0 1.1 1.5 V

Figure 1, Figure 2

Maximum Dynamic V

(Note 4)(Note 5)

OLV

Quiet Output

5.0 −0.6 −1.2 V

Figure 1, Figure 2

Minimum Dynamic V

(Note 4)(Note 5)

IHD

Minimum HIGH Level

5.0 1.9 2.2 V (Note 4)(Note 6)

Dynamic Input Voltage

ILD

Maximum LOW Level

5.0 1.2 0.8 V (Note 4)(Note 6)

Dynamic Input Voltage

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74ACTQ541

AC Electrical Characteristics

Note 7: Voltage Range 5.0 is 5.0V ± 0.5V Note 8: Skew is defined as t he absolute value of t he difference between the actual propagation delay for any two separate outputs of the same device. The

specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t

OSHL

) or LOW-to-HIGH (t

OSLH

). Parameter guarantee d by design.

Capacitance

Symbol Parameter

TA = +25°CT

= −40°C to +85°C

Units

(V)

= 50 pF CL = 50 pF

(Note 7) Min Typ Max Min Max

PLH

Propagation Delay

5.0

2.0 4.5 7.0 2.0 7.5 ns

PHL

Data to Output 2.0 5.5 7.0 2.0 7.5

PZH

Output Enable Time

5.0

2.0 5.0 9.0 2.0 9.5 ns

PZL

2.0 6.5 9.0 2.0 9.5

PHZ

Output Disable Time

5.0

1.5 5.5 7.5 1.5 8.0 ns

PLZ

1.5 5.5 7.5 1.5 8.0

OSHL

Output to Output 0.5 1.0 1.0

OSLH

Skew Data to Output (Note 8) 0.5 1.0 1.0

Symbol Parameter Typ Units Conditions

Input Capacitance 4.5 pF VCC = OPEN

Power Dissipation Capacitance 70 pF VCC = 5.0V

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74ACTQ541

FACT Noise Characteristics

The setup of a noise characteristics measurement is critical to the accuracy and repeatability of the tests. The following is a brief description of the setup used to measure the noise characteristics of FACT.

Equipment:

Hewlett Packard Model 8180A Word Generator PC-163A Test Fixture Tektronics Model 7854 Oscilloscope

Procedure:

1. Verify Test Fixture Loading: Standard Load 50 pF, 500Ω.

2. Deskew the HFS generator so that no two channels have greater than 15 0 ps skew between them. This requires that the oscilloscope be deskewed first. It is important to deskew the HFS generator channels before testing. This will ensure that the outputs sw itch simultaneously.

3. Terminate all inputs and outputs to ens ure pro per load ing of the outputs a nd that the input levels a re at the correct voltage.

4. Set the HFS ge nerato r to togg le all bu t one out put at a frequency of 1 MHz. Greater fre quencies will increa se DUT heating and effect the results of the measurement.

5. Set the HFS gene rator input lev els at 0V LOW a nd 3V HIGH for ACT devices and 0V LOW and 5V HIGH for AC devices. Verify levels with an oscilloscope.

OHV

and V

OLP

are measured with re s pect to ground reference.

Input pulses have t he following ch aracteristics: f = 1 MHz, t

= 3ns, tf = 3

ns, skew < 150 ps.

FIGURE 1. Quiet Output Noise Voltage Waveforms

OLP/VOLV

and V

OHP/VOHV

• Determine the quiet output pin that demonstrates the greatest noise levels. The worst case pin will usually be the furthest from the gr ound pin. Monitor th e o utp ut voltages using a 50Ω coaxi al cable p lugg ed into a standa rd SMB type connector on the te st fixture. Do not use an active FET probe.

• Measure V

OLP

and V

OLV

on the quiet output du ring the

worst case transition for active and enable. Measure V

OHP

and V

OHV

on the quiet output during the worst

case active and enable transition.

• Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements.

ILD

and V

IHD

• Monitor one of the switching outputs using a 50Ω coaxial cable plugged into a standard SMB type connec tor on the test fixture. Do not use an active FET probe.

• First increase the input LOW voltage level , V

, until the

output begins to oscillate or steps ou t a min of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds V

limits, or on output HIGH levels that

exceed V

limits. The input LOW voltage level at which

oscillation occurs is defined as V

ILD

• Next decrease the input HIGH voltage level, V

, until

the output begins to oscillate or step s out a min of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds V

limits, or on output HIGH levels that

exceed V

limits. The input HIGH voltage level at which

oscillation occurs is defined as V

IHD

• Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability on the measurements.

FIGURE 2. Simultaneous Switching Test Circuit

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74ACTQ541

Physical Dimensions inches (millimeters) unless otherwise noted

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

Package Number M20B

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74ACTQ541

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Package Number MTC20

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

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74ACTQ541 Quiet Series Octal Buffer/Line Driver with 3-STATE Outputs

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N20A

Fairchild does not assume any responsibility for use of any circuitry described , no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are dev ic es or syste ms which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provide d in the labe l ing, can be re asonably expected to result in a significant injury to the user.

2. A critical compo nent in any com ponen t of a life s upp ort device or system whose failure to perform can be reasonably expected to cause the failure of the l ife support device or system, or to affect its safety or effectiveness.

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