Datasheet 74ACTQ374SJX, 74ACTQ374SJ, 74ACTQ374SCX, 74ACTQ374SC, 74ACTQ374QSCX Datasheet (Fairchild Semiconductor)

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July 1989 Revised November 1999

74ACQ374 • 74ACTQ374 Quiet Series Octal D-Type Flip-Flop with 3-STATE Outputs

74ACQ374 • 74ACTQ374 Quiet Series Octal D-Type Flip-Flop

with 3-STATE Outputs

General Description

The ACQ/ACTQ37 4 is a high-speed, low-po wer octal Dtype flip-flop featuring sepa rate D-t ype inputs for each flipflop and 3-STATE outputs for bus-oriented app lications. A buffered Clock (CP) and Output Enable (OE

) are common

to all flip-flops. The ACQ/ACTQ374 utilizes FACT Quiet Series technol-

ogy to guarantee quiet output switching and improve dynamic threshold performance. FACT Quiet Series features GTO output control and undershoot corrector in addition to a split ground bus for superior performance.

Features

■ ICC and IOZ reduced by 5 0%

■ Guaranteed simultaneous switching noise level and

dynamic threshold performan ce

■ Guarante ed pin-to-pin skew AC performance

■ Improved latch-up immunity

■ Buffered positive edge-triggered cl ock

■ 3-STATE outputs drive bus lines or buffer memory

address registers

■ Outputs source/sink 24 mA

■ Faster prop delays than the standard AC/ACT374

Ordering Code:

Device also available in Tape and Reel. Specify by appending s uffix let te r “X” to the ordering code.

Connection Diagram Pin Descriptions

FACT, Qui et Series , FACT Quiet Series, an d GTO are trademarks of Fairchild Semiconductor Corporation.

Order Number Package Number Package Description

74ACQ374SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body 74ACQ374SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ACQ374PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide 74ACTQ374SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body 74ACTQ374SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ACTQ374QSC MQA20 20-Lead Quarter Size Outline Packag e (Q SOP ), JED EC MO -13 7, 0.15 0” Wide 74ACTQ374PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Pin Names Description

0–D7

Data Inputs CP Clock Pulse Input OE

3-STATE Output Enable Input O

0–O7

3-STATE Outputs

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74ACQ374 • 74ACTQ374

Logic Symbols

IEEE/IEC

Functional Description

The ACQ/ACTQ374 consists of eight edge-trigger ed flipflops with individual D- type inputs and 3-STATE true outputs. The buffered clock a nd buffered Output Enable a re common to all flip-flops. The eight flip-flops will sto re the state of their individ ual D-type inputs that mee t the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE

) LOW, the contents of the eight flip-flops are avai lable at th e outputs. When the OE

is HIGH, the outputs go to the high imped-

ance state. Operation of the OE

input does not affect the

state of the flip-flops.

Tr uth Table

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance



= LOW-to-HIGH Transition

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

Inputs Outputs

CP OE O



XXH Z

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74ACQ374 • 74ACTQ374

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: Absolute max imum ratings are those values beyond which da m age

to the device may occu r. The databook spe cificatio ns shou ld be met, wit hout exception, to ensure that the system de sign is relia ble over its p ower supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside datab ook s pecifications.

DC Electrical Characteristics for ACQ

Supply Voltage (VCC) −0.5V to +7.0V DC Input Diode Current (I

)

= −0.5V −20 mA

= VCC + 0.5V +20 mA

DC Input Voltage (V

) −0.5V to VCC + 0.5V

DC Output Diode Current (I

)

= −0.5V −20 mA

= VCC + 0.5V +20 mA

DC Output Voltage (V

) −0.5V to VCC + 0.5V

DC Output S ource

or Sink Current (I

) ±50 mA

DC V

or Ground Current

per Output Pin (I

or I

GND

) ±50 mA

Storage Temperature (T

STG

) −65°C to +150°C DC Latch-Up Source or Sink Current ±300 mA Junction Temperature (T

)

PDIP 140°C

Supply Voltage (V

) ACQ 2.0V to 6.0V ACTQ 4.5V to 5.5V

Input Voltage (V

)0V to V

Output Voltage (VO)0V to V

Operating Temperature (TA) −40°C to +85°C Minimum Input Edge Rate ∆V/∆t

ACQ Devices V

from 30% to 70% of V

VCC @ 3.0V, 4.5V, 5.5V 125 mV/ns

Minimum Input Edge Rate ∆V/∆t

ACTQ devices V

from 0.8V to 2.0V

@ 4.5V, 5.5V 125 mV/ns

Symbol Parameter

TA = +25°CTA = −40°C to +85°C

Units Conditions

(V) Typ Guaranteed Limits

Minimum HIGH Level 3.0 1.5 2.1 2.1 V

OUT

= 0.1V

Input Voltage 4.5 2.25 3.15 3.15 V or VCC − 0.1V

5.5 2.75 3.85 3.85

Maximum LOW Level 3.0 1.5 0.9 0.9 V

OUT

= 0.1V

Input Voltage 4.5 2.25 1.35 1.35 V or VCC − 0.1V

5.5 2.75 1.65 1.65

Minimum HIGH Level 3.0 2.99 2.9 2.9 Output Voltage 4.5 4.49 4.4 4.4 V I

OUT

= −50 µA

5.5 5.49 5.4 5.4 VIN = VIL or V

3.0 2.56 2.46 IOH = −12 mA

4.5 3.86 3.76 V I

= −24 mA

5.5 4.86 4.76 I

= −24 mA (Note 2)

Maximum LOW Level 3.0 0.002 0.1 0.1 Output Voltage 4.5 0.001 0.1 0.1 V I

OUT

= 50 µA

5.5 0.001 0.1 0.1

3.0 0.36 0.44 IOL = 12 mA

4.5 0.36 0.44 V IOL = 24 mA

5.5 0.36 0.44 IOL = 24 mA (Note 2)

IIN (Note 4) Maximum Input Leakage Current 5.5 ±0.1 ±1.0 µAVI = VCC, GND I

OLD

Minimum Dynamic 5.5 75 mA V

OLD

= 1.65V Max

OHD

Output Current (Note 3) 5.5 −75 mA V

OHD

= 3.85V Min

(Note 4) Maximum Quiescent Supply Current 5.5 4.0 40.0 µAVIN = VCC or GND

Maximum 3-STATE VI (OE) = VIL, V

Leakage Current 5.5 ±0.25 ±2.5 µAVI = VCC, GND

VO = VCC, GND

OLP

Quiet Output 5.0 1.1 1.5 V Figure 1, Figure 2 Maximum Dynamic V

(Note 5)(Note 6)

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74ACQ374 • 74ACTQ374

DC Electrical Characteristics for ACQ (Continued)

Note 2: All outputs loaded; thresholds on input assoc iat ed with output under tes t. Note 3: Maximum test duratio n 2. 0 ms, one output loaded at a time. Note 4: I

and ICC @ 3.0V are guaranteed to be less than or equa l to th e respective limit @ 5.5V VCC.

Note 5: DIP Package . Note 6: Max number of output s d ef ined as (n). Data inputs ar e driven 0V to 5V. One output @ GND. Note 7: Max number of data inputs (n) switching. (n−1) inputs switching 0V to 5V (ACQ). Input-under-test switching: 5V to threshold (V

ILD

0V to threshold (V

IHD

), f = 1 MHz.

DC Electrical Characteristics for ACTQ

Note 8: All outputs loaded; thresholds on input assoc iat ed with output under tes t. Note 9: Maximum test duratio n 2. 0 ms, one output loaded at a time. Note 10: DIP package. Note 11: Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output @ GND Note 12: Max number of data inp ut s (n) s w it c hing. (n−1) inputs switc hing 0V to 3V (ACTQ). Input -under-test switching: 3V to threshold (V

ILD

0V to threshold (V

IHD

), f = 1 MHz.

Symbol Parameter

TA = +25°CTA = −40°C to +85°C

Units Conditions

(V) Typ Guaranteed Limits

OLV

Quiet Output 5.0 −0.6 −1.2 V Figure 1, Figure 2 Minimum Dynamic V

(Note 5)(Note 6)

IHD

Minimum HIGH Level

5.0 3.1 3.5 V (Note 5)(Note 7)

Dynamic Input Voltage

ILD

Maximum LOW Level

5.0 1.9 1.5 V (Note 5)(Note 7)

Dynamic Input Voltage

Symbol Parameter

TA = +25°CTA = −40°C to +85°C

Units Conditions

(V) Typ Guaranteed Limits

Minimum HIGH Level 4.5 1.5 2.0 2.0

OUT

= 0.1V

Input Voltage 5.5 1.5 2.0 2.0 or VCC − 0.1V

Maximum LOW Level 4.5 1.5 0.8 0.8

OUT

= 0.1V

Input Voltage 5.5 1.5 0.8 0.8 or V

− 0.1V

Minimum HIGH Level 4.5 4.49 4.4 4.4

OUT

= −50 µA

Output Voltage 5.5 5.49 5.4 5.4

VIN = VIL or V

4.5 3.86 3.76 V IOH = −24 mA

5.5 4.86 4.76 I

= −24 mA (Note 8)

Maximum LOW Level 4.5 0.001 0.1 0.1

OUT

= 50 µA

Output Voltage 5.5 0.001 0.1 0.1

VIN = VIL or V

4.5 0.36 0.44 V IOL = 24 mA

5.5 0.36 0.44 IOL = 24 mA (Note 8)

(Note 4) Maximum Input Leakage Current 5.5 ±0.1 ±1.0 µAV

= VCC, GND

Maximum 3-STATE

5.5 ±0.25 ±2.5 µA

VI = VIL, V

Current VO = VCC, GND

CCT

Maximum

5.5 0.6 1.5 m A V

= VCC − 2.1V

ICC/Input (Note 4)

OLD

Minimum Dynamic 5.5 75 mA V

OLD

= 1.65V Max

OHD

Output Current (Note 8) 5.5 −75 mA V

OHD

= 3.85V Min

Maximum Quiescent

5.5 4.0 40.0 µA

VIN = V

(Note 4) Supply Current or GND V

OLP

Quiet Output

5.0 1.1 1.5 V

Figure 1, Figure 2

Maximum Dynamic V

(Note 10)(Note 11)

OLV

Quiet Output

5.0 −0.6 −1.2 V

Figure 1, Figure 2

Minimum Dynamic V

(Note 10)(Note 11)

IHD

Minimum HIGH Level Dynamic Input Voltage 5.0 1.9 2.2 V (Note 10)(Note 12)

ILD

Maximum LOW Level Dynamic Input Voltage 5.0 1.2 0.8 V (Note 10)(Note 12)

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74ACQ374 • 74ACTQ374

AC Electrical Characteristics for ACQ

Note 13: Voltage Ran ge 5.0 is 5.0V ± 0.5V

Voltage Range 3.3 is 3.3V ± 0.3V

Note 14: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the sam e d evice. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t

OSHL

) or LOW-to-HIGH (t

OSLH

). Parameter guaranteed by des ign.

AC Operating Requirements for ACQ

Note 15: Voltage Ran ge 5.0 is 5.0V ± 0.5V

Voltage Range 3.3 is 3.3V ± 0.3V

AC Electrical Characteristics for ACTQ

Note 16: Voltage Ran ge 5.0 is 5.0V ± 0.5V Note 17: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the sam e d evice. The

specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t

OSHL

) or LOW-to-HIGH (t

OSLH

). Parameter guaranteed by des ign.

TA = +25°CT

= −40°C to +85°C

Symbol Parameter (V)

= 50 pF CL = 50 pF

Units

(Note 13) Min Typ Max Min Max

MAX

Maximum Clock 3.3 75 70

MHz

Frequency 5.0 90 85

PLH

Propagation Delay 3.3 3.0 9.5 13.0 3.0 13.5

PHL

CP to O

5.0 2.0 6.5 8.5 2.0 9.0

PZL

Output Enable Time 3.3 3.0 9.5 13.0 3.0 13.5

PZH

5.0 2.0 6.5 8.5 2.0 9.0

PHZ

Output Disable Time 3.3 1.0 9.5 14.5 1.0 15.0

PLZ

5.0 1.0 8.0 9.5 1.0 10.0

OSHL

Output to Output Skew (Note 14) 3.3 1.0 1.5 1.5

OSLH

CP to O

5.0 0.5 1.0 1.0

TA = +25°CT

= −40°C to +85°C

Symbol Parameter (V)

CL = 50 pF CL = 50 pF

Units

(Note 15) Typ Guaranteed Minimum

Setup Time, HIGH or LOW 3.3 0 3.0 3.0

Dn to CP 5.0 0 3.0 3.0

Hold Time, HIGH or LOW 3.3 0 1.5 1.5

Dn to CP 5.0 2.0 1.5 1.5

CP Pulse Width, 3.3 2.0 4.0 4.0

HIGH or LOW 5.0 2.0 4.0 4.0

TA = +25°CT

= −40°C to +85°C

Symbol Parameter (V)

= 50 pF CL = 50 pF

Units

(Note 16) Min Typ Max Min Max

MAX

Maximum Clock

5.0 85 80 MHz

Frequency

PLH

Propagation Delay

5.0 2.0 7.0 9.0 2.0 9.5 ns

PHL

CP to O

PZL tPZH

Output Enable Time 5.0 2.0 7.5 9.0 2.0 9.5 ns

PHZ tPLZ

Output Disable Time 5.0 1.0 8.0 10.0 1.0 10.5 ns

OSHL

Output to Output Skew (Note 17)

5.0 0.5 1.0 1.0 ns

OSLH

CP to O

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74ACQ374 • 74ACTQ374

AC Operating Requirements for ACTQ

Note 18: Voltage Range 5.0 is 5.0V ± 0.5V

Capacitance

TA = +25°CT

= −40°C to +85°C

Symbol Parameter (V)

= 50 pF CL = 50 pF

Units

(Note 18) Typ Guaranteed Minimum

Setup Time, HIGH or LOW

5.0 0 3.0 3.0 ns

to CP

Hold Time, HIGH or LOW

5.0 0 1.5 1.5 ns

to CP

CP Pulse Width,

5.0 2.0 4.0 4.0 ns

HIGH or LOW

Symbol Parameter Typ Units Conditions

Input Capacitance 4.5 pF VCC = OPEN

Power Dissipation Capacitance 42.0 pF VCC = 5.0V

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74ACQ374 • 74ACTQ374

FACT Noise Characteristics

The setup of a noise characteristics measurement is critical to the accuracy and repeatability of the tests. The following is a brief description of the setup used to measure the noise characteristics of FACT.

Equipment:

Hewlett Packard Model 8180A Word Generator PC-163A Test Fixture Tektronics Model 7854 Oscilloscope

Procedure:

1. Verify Test Fixture Loading: Standard Load 50 pF, 500Ω.

2. Deskew the HFS ge nerator so that no two channels have greater than 150 ps skew between them. This requires that the oscilloscope be deskewed first. It is important to deskew the HFS generator channels before testing. This will ensure that the outputs switch simultaneously.

3. Terminate all inputs and outputs to ensure proper loading of the outputs and that the input levels are at the correct voltage.

4. Set the HFS gener ator to toggle al l but on e outpu t at a frequency of 1 MHz. Greater frequencies will increase DUT heating and effect the results of the measurement.

5. Set the HF S gen erator input le vels at 0V LO W and 3V HIGH for ACT devices and 0V LOW and 5V HIGH for AC devices. Verify levels with an oscilloscope.

Note 19: V

OHV

and V

OLP

are measured with respect to ground reference.

Note 20: Input pulses have the following characteristics: f = 1 MHz, t

= 3ns, tf = 3ns, skew < 150 ps.

FIGURE 1. Quiet Output Noise Voltage Waveforms

OLP/VOLV

and V

OHP/VOHV

• Determine the quiet output pin that demonstrates the greatest noise levels. The worst case pin will us ually be the furthest from th e g rou nd pin . Monitor the output vol tages using a 50Ω coaxial ca ble plug ged i nto a stand ard SMB type connector on the test fixture. Do not use an active FET probe.

• Measure V

OLP

and V

OLV

on the quiet output du ring the

worst case transition for active and enable. Measure V

OHP

and V

OHV

on the quiet output during the worst

case active and enable transition.

• Verify that the GND reference r ecorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements.

ILD

and V

IHD

• Monitor one of the switching outputs using a 50Ω coaxial cable plugged into a st andard SMB type connector on the test fixture. Do not use an active FET probe.

• First increase the input LOW voltage level, V

, until the

output begins to oscillate or steps o ut a min of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds V

limits, or on output HIGH levels that

exceed V

limits. The input LOW voltage level at which

oscillation occurs is defined as V

ILD

• Next decrease the input HIGH voltage level, V

, until

the output begins to osci llate or steps o ut a m in o f 2 ns . Oscillation is defined as noise on the output LOW level that exceeds V

limits, or on output HIGH levels that

exceed V

limits. The input HIGH voltage level at which

oscillation occurs is defined as V

IHD

• Verify that the GND reference r ecorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements.

FIGURE 2. Simultaneous Switching Test Circuit

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74ACQ374 • 74ACTQ374

Physical Dimensions inches (millimeters) unless otherwise noted

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Bod y

Package Number M20B

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74ACQ374 • 74ACTQ374

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M20D

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74ACQ374 • 74ACTQ374

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150” Wide

Package Number MQA20

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74ACQ374 • 74ACTQ374 Quiet Series Octal D-Type Flip-Flop with 3-STATE Outputs

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Package Number N20A

Fairchild does not assume any responsibility for use of any circuitry described , no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are dev ices or syste ms which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provide d in the labe l ing, can be re asonably expected to result in a significant injury to the user.

2. A critical compo nent in any com ponen t of a life s uppor t device or system whose failure to perform can be reasonably expected to cause the failure of the l ife support device or system, or to affect its safety or effectiveness.

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