Datasheet 74ACTQ16541SSC, 74ACTQ16541MTDX, 74ACTQ16541MTD, 74ACTQ16541CW Datasheet (Fairchild Semiconductor)

© 1999 Fairchild Semiconductor Corporation DS010936 www.fairchildsemi.com

June 1991
Revised November 1999

74ACTQ16541 16-Bit Buffer/Line Driver with 3-STATE Outputs

74ACTQ16541
16-Bit Buffer/Line Driver with 3-STATE Outputs

General Description

The ACTQ16541 contains sixteen non-inverting buffers
with 3-STATE outputs designed to be employed as a mem­ory and address driver, clock driver, or bus oriented trans­mitter/receiver. The device is byte controlled. Each byte
has separate 3-STATE control inputs which can be shorted
together for full 16-bit operation.

The ACTQ16541 utilizes Fairchild Quiet Series technol­ogy to guarantee quiet output switching and improved
dynamic threshold perf ormance. FACT Quiet Series fe a­tures GTO output control for superior performance.

Features

■ Utilizes Fairchild FACT Quiet Series technology

■ Guaranteed simultaneous switching noise level and

dynamic threshold performance

■ Guaranteed pin-to-pin output skew

■ Separate control logic for each byte

■ 16-bit version of the ACTQ541

■ Outputs source/sink 24 mA

■ Additional specs for Multiple Output Switching

■ Output loading specs for both 50 pF and 250 pF loads

Ordering Code:

Device also available in Tape and Reel. Specify by appending s uffix let te r “X” to the ordering code.

Logic Symbol

Pin Descriptions

Connection Diagram

FACT, Qui et Series , FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation

Order Number Package Number Package Description

74ACTQ16541SSC MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74ACTQ16541MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), MO-153, 6.1mm Wide

Pin Names Description

OE

n

Output Enable Input (Active LOW)

I

0–I15

Inputs

O

0–O15

Outputs

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74ACTQ16541

Functional Description

The ACTQ16541 contains sixteen non-inverting buffers
with 3-STATE standard outputs. The device is byte con­trolled with each by te functioning identically, but indepen­dent of the other. The control pin s can be sh orted togethe r
to obtain full 16-bit operation. The 3-STATE outputs are
controlled by an Outp ut Enable (OE

n

) input for each byte.

When OE

n

is LOW, the outputs are in 2-state mode. When

OE

n

is HIGH, the outputs are in the high impedance mode,

but this does not interfere w ith entering new data into the
inputs.

Tr uth Tables

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance

Logic Diagram

Inputs Outputs

OE

1

OE

2

I0–I

7

O0–O

7

LLH H
HXX Z
XHX Z
LLL L

Inputs Outputs

OE

3

OE

4

I8–I

15

O8–O

15

LLH H
HXX Z
XHX Z
LLL L

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74ACTQ16541

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: Absolute max imum rating s are those values beyond w hich damage

to the device may occu r. The databook spe cificatio ns shou ld be met, wit h­out exception to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specific at ions.

DC Electrical Characteristics

Note 2: All outputs loaded; thresholds associated with output under test.
Note 3: Maximum test duration 2.0 ms; one output loaded at a time.
Note 4: Worst case package.
Note 5: Maximum number of outputs that can switch simultaneously is n. (n − 1) outputs are switched LOW and one output held LOW.
Note 6: Maximum number of outputs that can switch simultaneously is n. (n − 1) outputs are switched HIGH and one output held HIGH.
Note 7: Maximum number of data inputs (n) switching. (n − 1) input switching 0V to 3V. Input under test switching 3V to threshold (V

ILD

).

Supply Voltage (VCC) −0.5V to +7.0V
DC Input Diode Current (I

IK

)

V

I

= −0.5V −20 mA

V

I

= VCC + 0.5V +20 mA

DC Output Diode Current (I

OK

)

V

O

= −0.5V −20 mA

V

O

= VCC + 0.5V +20 mA

DC Output Voltage (V

O

) −0.5V to VCC + 0.5V

DC Output Source/Sink Current (I

O

) ±50 mA

DC V

CC

or Ground Current

per Output Pin ±50 mA

Storage Temperature −65°C to +150°C

Supply Voltage (V

CC

) 4.5V to 5.5V

Input Voltage (V

I

)0V to V

CC

Output Voltage (VO)0V to V

CC

Operating Temperature (TA) −40°C to +85°C
Minimum Input Edge Rate (∆V/∆t) 125 mV/ns

V

IN

from 0.8V to 2.0V

V

CC

@ 4.5V, 5.5V

Symbol Parameter

V

CC

TA = +25°CTA = −40°C to +85°C

Units Conditions

(V) Typ Guaranteed Limits

V

IH

Minimum HIGH 4.5 1.5 2.0 2.0

V

V

OUT

= 0.1V

Input Voltage 5.5 1.5 2.0 2.0 or VCC − 0.1V

V

IL

Maximum LOW 4.5 1.5 0.8 0.8

V

V

OUT

= 0.1V

Input Voltage 5.5 1.5 0.8 0.8 or VCC − 0.1V

V

OH

Minimum HIGH 4.5 4.49 4.4 4.4

VI

OUT

= −50 µA

Output Voltage 5.5 5.49 5.4 5.4

VIN = VIL or V

IH

4.5 3.86 3.76 V IOH = −24 mA

5.5 4.86 4.76 IOH = −24 mA (Note 2)

V

OL

Maximum LOW 4.5 0.001 0.1 0.1

VI

OUT

= 50 µA

Output Voltage 5.5 0.001 0.1 0.1

VIN = VIL or V

IH

4.5 0.36 0.44 V IOL = 24 mA

5.5 0.36 0.44 I

OL

= 24 mA (Note 2)

I

OZ

Maximum 3-STATE

5.5 ±0.5 ±5.0 µA

VI = VIL, V

IH

Leakage Current VO = VCC, GND

I

IN

Maximum Input Leakage Current 5.5 ±0.1 ±1.0 µAVI = VCC, GND

I

CCT

Maximum ICC/Input 5.5 0.6 1.5 mA VI = VCC − 2.1V

I

CC

Max Quiescent Supply Current 5.5 8.0 80.0 µAVIN = VCC or GND

I

OLD

Minimum Dynamic

5.5

75 mA V

OLD

= 1.65V Max

I

OHD

Output Current (Note 3) −75 mA V

OHD

= 3.85V Min

V

OLP

Quiet Output

5.0 0.5 0.8 V

Figure 1, Figure 2

Maximum Dynamic V

OL

(Note 5)(Note 6)

V

OLV

Quiet Output

5.0 −0.5 −1.0 V

Figure 1, Figure 2

Minimum Dynamic V

OL

(Note 5)(Note 6)

V

OHP

Maximum

5.0

VOH +

1.0

VOH +

1.5

V

Figure 1, Figure 2

Overshoot (Note 4)(Note 6)

V

OHV

Minimum

5.0 VOH − 1.0 VOH − 1.8 V

Figure 1, Figure 2

VCC Droop (Note 4)(Note 6)

V

IHD

Minimum HIGH Dynamic Input Voltage Level 5.0 1.7 2.0 V (Note 4)(Note 7)

V

ILD

Maximum LOW Dynamic Input Voltage Level 5.0 1.2 0.8 V (Note 4)(Note 7)

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74ACTQ16541

AC Electrical Characteristics

Note 8: Voltage Range 5.0 is 5.0V ± 0.5V.

Extended AC Electrical Characteristics

Note 9: Voltage Range 5.0 is 5.0V ± 0.5V.
Note 10: Skew is defined as the absolu te valu e of the differe nce bet ween the actu al propag ation de lays for a ny two s eparat e outpu ts of the s ame devic e.

The specification ap plies to any ou tputs switc hing HIGH -to-LO W (t

OSHL

), LOW-to-HIGH (t

OSLH

), or any combin atio n swit ch ing LO W-to -HIGH an d/or HI GH-

to-LOW (t

OST

).

Note 11: This specification is gu aranteed but not tested. The limits apply to propagation delays for all paths des c ribed switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).

Note 12: This specification is gu aranteed but not tested. The lim its represen t propagation de lays with 250 p F load capacitors in place of the 5 0 pF load
capacitors in the standard AC load. This specification pertains to single output switching only.

Note 13: 3-STATE delays are load dominated and have been excluded from the datasheet.
Note 14: The Output Disable Time is dominated by the RC Network (500Ω, 250 pF) on the output and has been excluded from the datasheet.

Capacitance

V

CC

TA = +25°CT

A

= −40°C to +85°C

Symbol Parameter (V) C

L

= 50 pF CL = 50 pF Units

(Note 8) Min Typ Max Min Max

t

PLH

Propagation Delay

5.0

3.0 5.2 7.3 3.0 7.8
ns

t

PHL

Data to Output 2.5 4.8 7.3 2.5 7.8

t

PZH

Output Enable Time

5.0

2.6 5.0 7.4 2.6 7.9
ns

t

PZL

2.7 5.4 8.0 2.7 8.5

t

PHZ

Output Disable Time

5.0

2.7 5.6 8.3 2.7 8.7
ns

t

PLZ

2.4 5.2 7.9 2.4 8.4

TA = −40°C to +85°C

C

L

= 50 pF TA = −40°C to +85°C

Symbol Parameter

V

CC

16 Outputs Switching

CL = 250 pF

Units

(V) (Note 11) (Note 12)

(Note 9) Min Typ Max Min Max

t

PLH

Propagation Delay,

5.0

4.0 11.6 5.6 14.3
ns

t

PHL

Data to Output 3.4 9.6 4.8 13.1

t

PZH

Output Enable Time

5.0

3.3 10.1

(Note 13) n s

t

PZL

3.3 10.0

t

PHZ

Output Disable Time

5.0

4.3 10.1

(Note 14) n s

t

PLZ

3.8 9.6

t

OSHL

Pin to Pin Skew, HL

5.0 1.2 ns

(Note 10) Data to Output
t

OSLH

Pin to Pin Skew, LH

5.0 2.5 ns

(Note 10) Data to Output
t

OST

Pin to Pin Skew,

5.0 4.3 ns

(Note 10) LH/HL Data to Output

Symbol Parameter Typ Units Conditions

C

IN

Input Capacitance 4.5 pF VCC = 5.0V

C

PD

Power Dissipation Capacitance 30 pF VCC = 5.0V

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74ACTQ16541

FACT Noise Characteristics

The setup of a noise characteristics measurement is critical
to the accuracy and repeatability of the tests. The following
is a brief description of the setup used to measure the
noise characteristics of FACT.

Equipment:

Hewlett Packard Model 8180A Word Generator
PC-163A Test Fixture
Tektronics Model 7854 Oscilloscope

Procedure:

1. Verify Test Fixture Loading: Standard Load 50 pF,
500Ω.

2. Deskew the HFS generator so that no two channels
have greater than 150 ps skew between them. This
requires that the oscilloscope be deskewed first. It is
important to deskew the HFS generator channels
before testing. This will ensure that the outputs switch
simultaneously.

3. Terminate all inputs and outputs to ensure proper load­ing of the outputs and that the input levels are at the
correct voltage.

4. Set the HFS generator to togg le all bu t one ou tpu t at a
frequency of 1 MHz. Greater frequencies will increase
DUT heating and effect the results of the measure­ment.

5. Set the HFS gen erator input level s at 0V LOW a nd 3V
HIGH for ACT devices and 0V LOW and 5V HIGH for
AC devices. Verify levels with an oscilloscope.

Note A: V

OHV

and V

OLP

are measured with respect to ground reference.

Note B: Input pulses have the following characteristics: f =1 MHz,
t

r

=3ns, tf= 3 ns, skew < 150 ps.

FIGURE 1. Quiet Output Noise Voltage Waveforms

V

OLP/VOLV

and V

OHP/VOHV

:

• Determine the quiet output pin that demonstrates the
greatest noise levels. The worst case pin will us ually be
the furthest from th e g rou nd pin . Monitor the output vol t­ages using a 50Ω coaxial ca ble plug ged i nto a stand ard
SMB type connector on the test fixture. Do not use an
active FET probe.

• Measure V

OLP

and V

OLV

on the quiet output durin g the

worst case transition for active and enable. Measure
V

OHP

and V

OHV

on the quiet output during the worst

case for active and enable transition.

• Verify that the GND reference recorded on the oscillo­scope has not drifted to ensure the accuracy and repeat­ability of the measurements.

V

ILD

and V

IHD

:

• Monitor one of the switching outputs using a 50Ω coaxial
cable plugged into a st andard SMB type connector on
the test fixture. Do not use an active FET probe.

• First increase the input LOW voltage level, V

IL

, until the

output begins to oscillate or steps o ut a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds V

IL

limits, or on output HIGH levels that

exceed V

IH

limits. The input LOW voltage level at which

oscillation occurs is defined as V

ILD

.

• Next decrease the input HIGH voltage level, V

IH

, until

the output begins to osci llate or steps o ut a m in o f 2 ns .
Oscillation is defined as noise on the output LOW level
that exceeds V

IL

limits, or on output HIGH levels that

exceed V

IH

limits. The input HIGH voltage level at which

oscillation occurs is defined as V

IHD

.

• Verify that the GND reference recorded on the oscillo­scope has not drifted to ensure the accuracy and repeat­ability of the measurements.

FIGURE 2. Simultaneous Switching Test Circuit

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74ACTQ16541

Physical Dimensions inches (millimeters) unless otherwise noted

48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide

Package Number MS48A

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74ACTQ16541 16-Bit Buffer/Line Driver with 3-STATE Outputs

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

48-Lead Thin Shrink Sm all Ou tline Pa ck age (TS SO P), JE DE C MO-153, 6.1mm Wide

Package Number MTD48

Fairchild does not assume any responsibility for use of any circuitry described , no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:

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which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provide d in the labe l ing, can be re a­sonably expected to result in a significant injury to the
user.

2. A critica l compo nent in any compo nent o f a li fe supp ort
device or system whose failure to perform can be rea­sonably expected to cause the failure of the l ife support
device or system, or to affect its safety or effectiveness.

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