Datasheet 74ACTQ153SCX, 74ACTQ153SC, 74ACTQ153PC, 74ACTQ153CW Datasheet (Fairchild Semiconductor)
Page 1
July 1990
Revised May 1999
74ACTQ153 Quiet Series Dual 4-Input Multiplexer
© 1999 Fairchild Semiconductor Corporation DS010244.prf www.fairchildsemi.com
74ACTQ153
Quiet Series Dual 4-Input Multiplexer
General Description
The ACTQ153 is a high-speed dual 4-input multiplexer with
common select inputs and individual enable inputs for each
section. It can select two lines of data fro m four sources.
The two buffered outputs present data in the true (noninverted) form. In addition to multiplexer operation, the
ACTQ153 can act as a function generat or and generate
any two functions of three variables.
Features
■ Outputs source/sink 24 mA
■ ACTQ153 has TTL-compatible inputs
■ Guaranteed simultaneous switching noise level and
dynamic threshold performance
■ Guarante ed pin-to-pi n skew AC per formance
■ Improved latch-up immunity
Ordering Code:
Device also available in Tape and Reel. Specify by appending s uffix let te r “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Pin Descriptions
FACT, FACT Quiet Serie s , and GTO are trademarks of F airchild Semiconductor Corporation.
Order Number Package Number Package Description
74ACTQ153SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74ACTQ153PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Pin Names Description
I
0a
- 1
3a
Side A Data Inputs
I
0b
- 1
3b
Side B Data Inputs
S
0
, S
1
Common Select Inputs
E
a
Side A Enable Input
E
b
Side B Enable Input
Z
a
Side A Output
Z
b
Side B Output
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74ACTQ153
Functional Description
The ACTQ153 is a dual 4-input multip lexer. It can select
two bits of data from up to four sources under the control of
the common Select inputs (S
0
, S1). The two 4-input multi-
plexer circuits have indi vi d ua l ac t iv e- L OW E n ab les ( E
a
, Eb)
which can be used to strobe the outputs independently.
When the Enables (E
a
, Eb) are HIGH, the corre sponding
outputs (A
z
, Zb) are forced LOW. The ACTQ153 is the logic
implementation of a 2-pole , 4-position switch, where the
position of the switch is determined by the logic levels supplied to the Select input s. The logic equatio ns for the outputs are shown below.
Z
a
= Ea • (I0a • S1 • S0 + I1a • S1 • S0 +
I
2a
• S1 •S0 + I3a • S1 • S0)
Z
b
= Eb • (I0b • S1 • S0 • I1b • S1 • S0 +
I
2b
• S1 • S0 +I3b • S1 • S0)
Tr uth Table
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Logic Diagram
Please note that this diagram is provided only f or t he understanding of lo gic operations and should not be used to estimate propagation delays.
Select
Inputs
Inputs (a or b) Outputs
S
0S1
E I0I1I2I
3
Z
XXHXXXX L
LLLLXXX L
LLLHXXX H
HLLXLXX L
HLLXHXX H
LHLXXLX L
LHLXXHX H
HHLXXXL L
HHLXXXH H
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74ACTQ153
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power
supply, temperature, and ou tput/inp ut load ing vari ables. Fairchild does n ot
recommend operat ion of FACT circuits outside dat abook specifications.
DC Electrical Characteristics
Note 2: All outputs loaded; thresholds on inpu t as s oc iated with output under te s t .
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Supply Voltage (VCC) −0.5V to +7.0V
DC Input Diode Current (I
IK
)
V
I
= −0.5V −20 mA
V
I
= VCC + 0.5V +20 mA
DC Input Voltage (V
I
) −0.5V to VCC + 0.5V
DC Output Diode Current (I
OK
)
V
O
= −0.5V −20 mA
V
O
= VCC + 0.5V +20 mA
DC Output Voltage (V
O
) −0.5V to VCC + 0.5V
DC Output Source
or Sink Current (I
O
) ±50 mA
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
) ±50 mA
Storage Temperature (T
STG
) −65°C to +150°C
DC Latch-Up Source or Sink Current ±300 mA
Junction Temperature (T
J
)
PDIP 140°C
Supply Voltage (V
CC
) 4.5V to 5.5V
Input Voltage (V
I
)0V to V
CC
Output Voltage (VO)0V to V
CC
Operating Temperature (TA) −40°C to +85°C
Minimum Input Edge Rate ∆V/∆t
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V 125 mV/ns
Symbol Parameter
V
CC
TA = +25°CT
A
= −40°C to +85°C
Units Conditions
(V) Typ Guaranteed Limits
V
IH
Minimum HIGH Level 4.5 1.5 2.0 2.0
V
V
OUT
= 0.1V
Input Voltage 5.5 1.5 2.0 2.0 or VCC − 0.1V
V
IL
Maximum LOW Level 4.5 1.5 0.8 0.8
V
V
OUT
= 0.1V
Input Voltage 5.5 1.5 0.8 0.8 or VCC − 0.1V
V
OH
Minimum HIGH Level 4.5 4.49 4.4 4.4
V
I
OUT
= −50 µA
Output Voltage 5.5 5.49 5.4 5.4
V
VIN = VIL or VIH
4.5 3.86 3.76 IOH = −24 mA
5.5 4.86 4.76 IOH = −24 mA (Note 2)
V
OL
Maximum LOW Level 4.5 0.001 0.1 0.1
V
I
OUT
= 50 µA
Output Voltage 5.5 0.001 0.1 0.1
V
VIN = VIL or V
IH
4.5 0.36 0.44 IOL = 24 mA
5.5 0.36 0.44 IOL = 24 mA (Note 2)
I
IN
Maximum Input
5.5 ±0.1 ±1.0 µAVI = VCC, GND
Leakage Current
I
CCT
Maximum
5.5 0.6 1.5 µAVI = VCC − 2.1V
ICC/Input
I
OLD
Minimum Dynamic 5.5 75 mA V
OLD
= 1.65V Max
I
OHD
Output Current (Note 3) 5.5 −75 mA V
OHD
= 3.85V Min
I
CC
Maximum Quiescent
5.5 8.0 80.0 µA
VIN = V
CC
Supply Current or GND
V
OLP
Maximum HIGH Level
5.0 1.1 1.5 V
Figure 1Figure 2
Output Noise (Note 4)(Note 5)
V
OLV
Maximum LOW Level
5.0 −0.6 −1.2 V Figure 1Figure 2
Output Noise
V
IHD
Minimum HIGH Level
5.0 1.9 2.2 V (Note 4)(Note 6)
Dynamic Input Voltage
V
ILD
Maximum LOW Level
5.0 1.2 0.8 V (Note 4)(Note 6)
Dynamic Input Voltage
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74ACTQ153
DC Electrical Characteristics (Continued)
Note 4: Worst case package.
Note 5: Max number of outputs defined as (n). Data Inputs are driven 0V to 5V. One Data Input @ V
IN
= GND.
Note 6: Max number of Data Inputs (n) switc hing. (n−1) inputs switching 0V to 5V. Input-under-test switching:
5V to threshold (V
ILD
), 0V to threshold (V
IHD
), f = 1 MHz.
AC Electrical Characteristics
Note 7: Voltage Range 5.0 is 5. 0V ± 0.5V
Capacitance
Symbol Parameter
V
CC
TA = +25°CT
A
= −40°C to +85°C
Units
(V)
CL = 50 pF CL = 50 pF
(Note 7) Min Typ Max Min Max
t
PLH
Propagation Delay
5.0 3.0 7.0 11.5 2.0 13.5 ns
Sn to Z
n
t
PHL
Propagation Delay
5.0 3.0 7.0 11.5 2.5 13.5 ns
Sn to Z
n
t
PLH
Propagation Delay
5.0 2.0 6.5 10.5 2.0 12.5 ns
En to Z
n
t
PHL
Propagation Delay
5.03.06.09.52.511.0ns
En to Z
n
t
PLH
Propagation Delay
5.02.55.59.52.011.0ns
In to Z
n
t
PHL
Propagation Delay
5.02.05.59.52.011.0ns
In to Z
n
Symbol Parameter Typ Units Conditions
C
IN
Input Capacitance 4.5 pF VCC = 5.0V
C
PD
Power Dissipation Capacitance 65.0 pF VCC = 5.0V
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74ACTQ153
FACT Noise Characteristics
The setup of a noise characteristics measurement is critical
to the accuracy and repeatability of the tests. The following
is a brief description of the setup used to measure the
noise characteristics of FACT.
Equipment:
Hewlett Packard Model 8180A Word Generator
PC-163A Test Fixture
Tektronics Model 7854 Oscilloscope
Procedure:
1. Verify Test Fixture Loading: Standard Load 50 pF,
500Ω.
2. Deskew the HFS generator so tha t no two channels
have greater than 150 ps skew between them. This
requires that the oscilloscope be deskewed first. It is
important to deskew the HFS generator channels
before testing. This will ensure that the outputs switch
simultaneously.
3. Terminate all inputs and outputs to ensure proper loading of the outputs and that the input levels are at the
correct voltage.
4. Set the HFS generator to toggle all but on e outpu t at a
frequency of 1 MHz. Greater frequencies will increase
DUT heating and effect the results of the measurement.
5. Set the HFS generator input level s at 0V LOW and 3V
HIGH for ACT device s and 0V LOW and 5 V HIGH for
AC devices. Verify levels with an oscilloscope.
Note 8: V
OHV
and V
OLP
are measured with re s pec t t o ground reference.
Note 9: Input pulses have the following characteristics: f = 1MHz, t
r
= 3ns,
t
f
= 3 ns, skew < 150 ps.
FIGURE 1. Quiet Output Noise Voltage Waveforms
V
OLP/VOLV
and V
OHP/VOHV
:
• Determine the quiet output pin that demonstrates the
greatest noise levels. The worst case pin will us ually be
the furthest from the g rou nd pi n . Mo nito r t he output voltages using a 50Ω coaxial ca ble plug ged i nto a sta ndard
SMB type connector on the test fixture. Do not use an
active FET probe.
• Measure V
OLP
and V
OLV
on the quiet output du ring the
worst case transition for active and enable. Measure
V
OHP
and V
OHV
on the quiet output during the worst
case active and enable transition.
• Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements.
V
ILD
and V
IHD
:
• Monitor one of the switching outputs using a 50Ω coaxial
cable plugged into a st andard SMB type connector on
the test fixture. Do not use an active FET probe.
• First increase the input LOW voltage level, V
IL
, until the
output begins to oscillate or steps o ut a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds V
IL
limits, or on output HIGH levels that
exceed V
IH
limits. The input LOW voltage level at which
oscillation occurs is defined as V
ILD
.
• Next decrease the input HIGH voltage level, V
IH
, until
the output begins to oscilla te or steps o ut a m in of 2 ns .
Oscillation is defined as noise on the output LOW level
that exceeds V
IL
limits, or on output HIGH levels that
exceed V
IH
limits. The input HIGH voltage level at which
oscillation occurs is defined as V
IHD
.
• Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements.
FIGURE 2. Simultaneous Switching Test Circuit
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74ACTQ153
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M20B
Page 7
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
74ACTQ153 Quiet Series Dual 4-Input Multiplexer
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are dev ic es or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided i n the labe li ng, can be re asonably expected to result in a significant injury to the
user.
2. A critical componen t in any com ponent o f a l ife supp ort
device or system whose failu re to perform can b e reasonably expected to c ause th e fa i lure of the li fe s upp or t
device or system, or to affect its safety or effectiveness.
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N20A
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