Datasheet 74ACTQ00SCX, 74ACTQ00SC, 74ACTQ00PC, 74ACTQ00MTCX, 74ACTQ00MTC Datasheet (Fairchild Semiconductor)

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August 1990 Revised April 1999

74ACTQ00 Quiet Series Quad 2-Input NAND Gate

General Description

The ACTQ00 contain s four 2-input NAND gates and uti lizes Fairchild FACT Quiet Series technology to guarantee quiet output switching and improve dynamic threshold performance FACT Quiet Series features GTO output control and undershoot corrector in addition to a split ground bus for superior ACMOS performance.

Features

■ ICC reduced by 50%

■ Guaranteed simultaneous switching noise level and

dynamic threshold performance

■ Improved latch-up immunity

■ Outputs source/sink 24 mA

■ Has TTL-com patible inputs

Ordering Code:

Device also available in Tape and Reel. Specify by appending s uffix let te r “X” to the ordering code .

Logic Symbol

IEEE/IEC

Connection Diagram

Pin Assignment for

DIP and SOIC

Pin Descriptions

FACT, Quiet S eries, FACT Quiet Series, and GTO are trademarks of Fairchild Sem ic onductor Corporation.

Order Number Package Number Package Description

74ACTQ00SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body 74ACTQ00PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Pin Names Description

, B

Inputs

Outputs

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74ACTQ00

Absolute Maximum Ratings(Note 1)

Recommended Operating Conditions

Note 1: Absolute maximum ratings are those values beyond which damage

to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its pow er supply, temperature, and ou tput/inp ut loadi ng varia bles. Fairchild does no t

DC Electrical Characteristics

Note 2: All outputs loaded; thresholds on input associated wit h output under test. Note 3: Maximum te st duration 2.0 ms, one ou t put loaded at a time. Note 4: DIP package. Note 5: Max number of outputs defined a s (n ). D at a inputs are 0V to 3V. One output @ GND . Note 6: Max number of data inputs (n) switching. (n−1) inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (V

ILD

0V to threshold (V

IHD

), f = 1 MHz.

Supply Voltage (VCC) −0.5V to +7.0V DC Input Diode Current (I

)

= −0.5V −20 mA

= VCC + 0.5V +20 mA

DC Input Voltage (V

) −0.5V to VCC + 0.5V

DC Output Diode Current (I

)

= −0.5V −20 mA

= VCC + 0.5V +20 mA

DC Output Voltage (V

) −0.5V to VCC + 0.5V

DC Output Source

or Sink Current (I

) ±50 mA

DC V

or Ground Current

per Output Pin (I

or I

GND

) ±50 mA

Storage Temperature (T

STG

) −65°C to +150°C

DC Latch-up Source

or Sink Current ±300 mA

Junction Temperature (T

)

PDIP 140°C

Supply Voltage (V

) 4.5V to 5.5V

Input Voltage (V

) 0V to V

Output Voltage (VO) 0V to V

Operating Temperature (TA) −40°C to +85°C Minimum Input Edge Rate (∆V/∆t)

from 0.8V to 2.0V 125 mV/ns

@ 4.5V, 5.5V

Symbol Parameter

TA = +25°CTA = −40°C to +85°C

Units Conditions

(V) Typ Guaranteed Limits

Minimum HIGH Level 4.5 1.5 2.0 2.0 V V

OUT

= 0.1V

Input Voltage 5.5 1.5 2.0 2.0 or VCC − 0.1V

Maximum LOW Level 4.5 1.5 0.8 0.8 V V

OUT

= 0.1V

Input Voltage 5.5 1.5 0.8 0.8 or VCC − 0.1V

Minimum HIGH Level 4.5 4.49 4.4 4.4 V I

OUT

= −50 µA

Output Voltage 5.5 5.49 5.4 5.4

VIN = VIL or V

4.5 3.86 3.76 IOH = −24 mA

5.5 4.86 4.76 V IOH = −24 mA (Note 2)

Maximum LOW Level 4.5 0.001 0.1 0.1 V I

OUT

= 50 µA

Output Voltage 5.5 0.001 0.1 0.1

VIN = VIL or V

4.5 0.36 0.44 IOL = 24 mA

5.5 0.36 0.44 V IOL = 24 mA (Note 2)

Maximum Input Leakage Current 5.5 ±0.1 ±1.0 µAVI = VCC, GND

CCT

Maximum ICC/Input 5.5 0.6 1.5 mA V I = VCC − 2.1V

OLD

Minimum Dynamic 5.5 75 mA V

OLD

= 1.65V Max

OHD

Output Current (Note 3) 5.5 −75 mA V

OHD

= 3.85V Min

Maximum Quiescent Supply Current 5.5 2.0 20.0 µAVIN = VCC or GND

OLP

Quiet Output Maximum Dynamic 5.0 1.1 1.5 V Figure 1, Figure 2 V

(Note 4)(Note 5)

OLV

Quiet Output Minimum Dynamic 5.0 −0.6 −1.2 V Figure 1, Figure 2 V

(Note 4)(Note 5)

IHD

Minimum HIGH Level Dynamic Input Voltage

5.0 1.9 2.2 V (Note 4)(Note 6)

ILD

Maximum LOW Level Dynamic Input Voltage

5.0 1.2 0.8 V (Note 4)(Note 6)

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74ACTQ00

AC Electrical Characteristics

Note 7: Voltage Range 5.0 is 5.0V ±0.5V. Note 8: Skew is def ined as the absol ut e v alue of the differenc e between the actu al propagation del ay f or any two separat e outputs of the same device. The

specification applies t o any outputs switching in the same direction , ei th er HIGH to LOW (t

OSHL

) or LOW to HIGH (t

OSLH

). Parameter guaranteed by design.

Capacitance

TA = +25°CT

= −40°C to +85°C

Symbol Parameter (V)

CL = 50 pF CL = 50 pF

Units

(Note 7) Min Typ Max Min Max

PLH

Propagation Delay 5.0 2.0 7.5 2.0 8.0 ns Data to Output

PHL

Propagation Delay 5.0 2.0 7.5 2.0 8.0 ns Data to Output

OSHL

Output to Output 5.0 0.5 1.0 1.0 ns

OSLH

Skew (Note 8)

Symbol Parameter Typ Units Conditions

Input Capacitance 4.5 pF VCC = OPEN

Power Dissipation Capacitance 74 pF VCC = 5.0V

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74ACTQ00

FACT Noise Characteristics

The setup of a noise characteristics measurement is critical to the accuracy and repeatability of the tests. The following is a brief description of the setup used to measure the noise characteristics of F ACT.

Equipment:

Hewlett Packard Model 8180A Word Generator PC-163A Test Fixture Tektronics Model 7854 Oscilloscope

Procedure:

1. Verify Test Fixture Loading: Standard Load 50 pF, 500Ω.

2. Deskew the HFS generator so that no two channels have greater than 15 0 ps skew between them. This requires that the oscilloscope be deskewed first. It is important to deskew the word generator channels before testing. This will ensure that the outputs sw itch simultaneously.

3. Terminate all inputs and outputs to ensure pro per load ing of the outputs a nd that the input levels a re at the correct voltage.

4. Set the HFS gener ator to to ggle al l but one output at a frequency of 1 MHz. Greate r frequencies will increa se DUT heating and effect the results of the measurement.

5. Set the HFS gene rator input l evels at 0V LOW a nd 3V HIGH for ACT devices and 0V LOW and 5V HIGH for AC devices. Verify levels with an oscilloscope

Note 9: V

OHV

and V

OLP

are measured with re sp ec t to ground reference.

Note 10: Input pul ses have the followin g characteristics: f = 1 MHz, t

3 ns, t

= 3 ns, skew < 150 ps.

FIGURE 1. Quiet Output Noise Voltage Waveforms

OLP/VOLV

and V

OHP/VOHV

• Determine the quiet output pin that demonstrates the greatest noise levels. The worst case pin will usually be the furthest from the gr ou nd pi n. Mo nito r the output voltages using a 50Ω coaxi al cable p lugg ed into a standa rd SMB type connector on the te st fixture. Do not use an active FET probe.

• Measure V

OLP

and V

OLV

on the quiet output du ring the

worst case transition for active and enable. Measure V

OHP

and V

OHV

on the quiet output during the worst

case active and enable transition.

• Verify t hat the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements.

ILD

and V

IHD

• Monitor one of the switching outputs using a 50Ω coaxial cable plugged into a sta ndard SMB type connector on the test fixture. Do not use an active FET probe.

• First increase the input LOW voltage level, V

, until the

output begins to oscillate or steps out a min of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds V

limits, or on output HIGH levels that

exceed V

limits. The input LOW voltage level at which

oscillation occurs is defined as V

ILD

• Next decrease the input HIGH voltage level.V

until the

output begins to oscillate or steps out a mine of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds V

limits, or on output HIGH levels that

exceed V

limits. The input HIGH voltage level at which

oscillation occurs is defined as V

IHD

• Verify t hat the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements.

FIGURE 2. Simultaneous Switching Test Circuit

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74ACTQ00

Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body

Package Number M14A

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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

74ACTQ00 Quiet Series Quad 2-Input NAND Gate

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or syste ms which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant inju ry to the user.

2. A critical component i n any compon ent of a lif e support device or system whose failu re to perform can be reasonably expected to ca use the fa i lure of the life su pp ort device or system, or to affect its safety or effectiveness.

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP) JEDEC MS-001, 0.300” Wide

Package Number N14A