Datasheet 74ACT652SPC, 74ACT652SCX, 74ACT652SC, 74ACT652MTCX, 74ACT652MTC Datasheet (Fairchild Semiconductor)

© 2000 Fairchild Semiconductor Corporation DS500310 www.fairchildsemi.com

August 1999
Revised September 2000

74ACT652 Transceiver/Register

74ACT652
Transceiver/Register

General Description

The ACT652 consists of bus transceiver circuits with D­type flip-flops, and control circuitry arranged for multiplexed
transmission of data directly from the input bus or from
internal registers. Data on the A or B bus will be clocked
into the registers a s the appropr iate clock pin g oes to the
HIGH logic level. Output Enable pins (OEAB, OEBA

) are

provided to control the transceiver function.

Features

■ Independent registers for A and B buses

■ Multiplexed real-time and stored data

■ Outputs source/sink 24 mA

■ TTL-compatible inputs

Ordering Code:

Device also available in Tape and Reel. Specify by appending s uffix let te r “X” to the ordering code.

Logic Symbols

IEEE/IEC

Connection Diagram

Pin Descriptions

FACT is a trademark of Fairchild Semiconductor Corporation.

Order Number Package Number Package Description

74ACT652SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74ACT652MTC MTC24 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT652SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Pin Names Description

A

0–A7

, B0–B7A and B Inputs/3-STATE Outputs
CPAB, CPBA Clock Inputs
SAB, SBA Select Inputs
OEAB, OEBA

Output Enable Inputs

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74ACT652

Function Table

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial



= LOW-to-HIGH Clo c k Transi ti on

Note 1: The data output fu nction s may b e enable d or di sabled b y variou s signa ls at O EAB or O EBA

inputs. Data input functions are always enabled, i.e.,

data at the bus pins w ill be stored on every LOW-to -H I GH t ransition on the clock inp ut s.

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

Inputs Inputs/Outputs (Note 1) Operating Mode

OEAB OEBA

CPAB CPBA SAB SBA A0 thru A7B0 thru B

7

L H H or L H or L X X Input Input Isolation
LH



X X Store A and B Data

XH



H or L X X Input Not Specified Store A, Hold B

HH



X X Input Outp ut Store A in Both Registers

LXH or L



X X Not Specified Input Hold A, Store B

LL



X X Output Input Store B in Both Registers
L L X X X L Output Input Real-Time B Data to A Bus
L L X H or L X H Store B Data to A Bus
H H X X L X Input Output Real-Time A Data to B Bus
H H H or L X H X Stored A Data to B Bus
H L H or L H or L H H Output Output Stored A Data to B Bus and

Stored B Data to A Bus

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74ACT652

Functional Description

In the transceiver mode , data present a t the HIGH impe d­ance port may be sto red in either the A or B register or
both.

The select (SAB, SBA) controls can multiplex stored and
real-time.

The examples in Figure 1 de monstr ate the fo ur funda men­tal bus-management func tions that can be perfor med with
the Octal bus transceivers and receivers.

Data on the A or B data bus, or both can be stored in the
internal D-type flip -flop by LOW to HIGH tr ansitions at the
appropriate Clock Inp uts (CPAB, CPBA) regardless of the
Select or Output Enable Inputs. When SAB and SBA are in
the real time transfer m od e, it is a lso po ssibl e to sto re d ata
without using the internal D-type flip-flops by simulta­neously enabling OEAB and OEBA

. In this configuration
each Output reinforces its Input. Thu s when all other data
sources to the two sets of bus lin es are in a HIGH imp ed­ance state, each set of bus lines will remain at its last state.

FIGURE 1.

Note A: Real-Time Note B: Real-Time

Transfer Bus B to Bus A Transfer Bus A to Bus B

OEAB OEBA

CPAB CPBA SAB SBA OEAB OEBA CPAB CPBA SAB SBA

LLXXXL HHXXLX

Note C: Storage Note D: Transfer Storage

Data to A or B

OEAB OEBA

CPAB CPBA SAB SBA OEAB OEBA CPAB CPBA SAB SBA

XH



X X X H L H or L H or L H H

LXX



XX

LH



XX

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74ACT652

Absolute Maximum Ratings(Note 2) Recommended Operating

Conditions

Note 2: Absolute maximum ratings are those values beyond which damage

to the device may occur. The databook specifications should be met, with­out exception, to ensure that the system design is reliable over its power
supply, temperature, and ou tput/inp ut loadi ng varia bles. Fairchild does no t
recommend operat ion of FACT circuits outside da t abook specifications.

DC Electrical Characteristics

Note 3: All outputs loaded; thresholds on input assoc iat ed with output under tes t.
Note 4: Maximum test duratio n 2. 0 ms, one output loaded at a time.

Supply Voltage (VCC) −0.5V to +7.0V
DC Input Diode Current (I

IK

)

V

I

= −0.5V −20 mA

V

I

= VCC + 0.5V +20 mA

DC Input Voltage (V

I

) −0.5V to VCC + 0.5V

DC Output Diode Current (I

OK

)

V

O

= −0.5V −20 mA

V

O

= VCC + 0.5V +20 mA

DC Output Voltage (V

O

) −0.5V to VCC + 0.5V

DC Output Source

or Sink Current (I

O

) ± 50 mA

DC V

CC

or Ground Current

per Output Pin (I

CC

or I

GND

) ± 50 mA

Storage Temperature (T

STG

) −65°C to +150°C

DC Latch-Up Source

or Sink Current ± 300 mA

Junction Temperature (T

J

)

PDIP 140

°C

Supply Voltage (V

CC

) 4.5V to 5.5V

Input Voltage (V

I

) 0V to V

CC

Output Voltage (VO) 0V to V

CC

Operating Temperature (TA) −40°C to +85°C
Minimum Input Edge Rate

∆V/∆t

V

IN

from 0.8V to 2.0V

V

CC

@ 4.5V, 5.5V 125 mV/ns

Symbol Parameter

V

CC

TA = +25°CT

A

= −40°C to +85°C

Units Conditions

(V) Typ Guaranteed Limits

V

IH

Minimum HIGH Level 4.5 1.5 2.0 2.0

V

V

OUT

= 0.1V

Input Voltage 5.5 1.5 2.0 2.0 or V

CC

− 0.1V

V

IL

Maximum LOW Level 4.5 1.5 0.8 0.8

V

V

OUT

= 0.1V

Input Voltage 5.5 1.5 0.8 0.8 or VCC − 0.1V

V

OH

Minimum HIGH Level 4.5 4.49 4.4 4.4

VI

OUT

= −50 µA

Output Voltage 5.5 5.49 5.4 5.4

VIN = VIL or V

IH

4.5 3.86 3.76 V IOH = −24 mA

5.5 4.86 4.76 I

OH

= −24 mA (Note 3)

V

OL

Maximum LOW Level 4.5 0.001 0.1 0.1

VI

OUT

= 50 µA

Output Voltage 5.5 0.001 0.1 0.1

VIN = VIL or V

IH

4.5 0.36 0.44 V IOL = 24 mA

5.5 0.36 0.44 IOL = 24 mA (Note 3)

I

IN

Maximum Input

5.5 ± 0.1 ± 1.0 µAVI = VCC, GND

Leakage Current

I

OZT

Maximum I/O

5.5 ± 0.6 ± 6.0 µA

VI = VIL, V

IH

Leakage Current VO = VCC, GND

I

CCT

Maximum ICC/Input 5.5 0.6 1.5 mA VI = VCC − 2.1V

I

OLD

Minimum Dynamic 5.5 75 mA V

OLD

= 1.65V Max

I

OHD

Output Current (Note4) 5.5 −75 mA V

OHD

= 3.85V Min

I

CC

Maximum Quiescent

5.5 8.0 80.0 µAVIN = VCC or GND

Supply Current

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74ACT652

AC Electrical Characteristics

Note 5: Voltage Range 5.0 is 5.0V ± 0.5V.

Capacitance

V

CC

TA = +25°CT

A

= −40°C to +85°C

Symbol Parameter (V)

C

L

= 50 pF CL = 50 pF

Units

(Note 5) Min Typ Max Min Max

f

MAX

Max. Clock Frequency 5.0 MHz

t

PLH

Propagation Delay

5.0 2.0 7.0 9.5 2.0 10.0 ns

t

PHL

Clock to Bus

t

PLH

Propagation Delay

5.0 2.0 6.5 9.0 2.0 9.5 ns

t

PHL

Bus to Bus

t

PLH

Propagation Delay

5.0 2.5 6.5 10.0 2.5 10.5 ns

t

PHL

SBA or SAB to A or B

t

PZH

Enable Time

5.0 2.0 7.0 10.5 2.0 11.0

ns

t

PZL

OEBA to A (Note 5)

t

PHZ

Disable Time

5.0 1.0 5.0 8.0 1.0 8.5

t

PLZ

OEBA to A (Note 5)

t

PZH

Enable Time

5.0 2.0 7.0 10.5 2.0 11.0

t

PZL

OEAB to B

t

PHZ

Disable Time

5.0 1.0 5.0 8.0 1.0 8.5 ns

t

PLZ

OEAB to B

ts(H) Setup Time, HIGH or

5.0 3.0 3.0 ns

ts(L) LOW, Bus to Clock
th(H) Hold Time, HIGH or

5.0 1.5 1.5 ns

th(L) L OW, Bus to Clock
t

w

(H) Clock Pulse Width

5.0 4.0 4.0 ns

t

w

(L) HIGH or LOW

Symbol Parameter Typ Units Conditions

C

IN

Input Capacitance 4.5 pF VCC = 5.0V

C

PD

Power Dissipation Capacitance 54 pF VCC = 5.0V

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74ACT652

Physical Dimensions inches (millimeters) unless otherwise noted

24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

Package Number M24B

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74ACT652

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

24-Lead Thin Shrink Sm all Ou tline Pa ck age (TS SO P), JE DE C MO-153, 4.4mm Wide

Package Number MTC24

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74ACT652 Transceiver/Register

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N24C

Fairchild does not assume any responsibility for use of any circuitr y described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea­sonably expected to result in a significant inju ry to the
user.

2. A critical component in any compon ent of a lif e supp ort
device or system whose failure t o perform can be rea­sonably expected to ca use the failure of the life supp ort
device or system, or to affect its safety or effectiveness.

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