The ACT574 is an advanced high-speed CMOS
OCTAL D-TYPE FLIP FLOP with 3 STATE
OUTPUT NON INVERTING fabricated with
sub-micron silicon gate and double-layer metal
wiringC
These 8 bit D-Type flip-flops are controlled by a
clockinput (CK)and an output enable input (OE).
On the positive transition of the clock, the Q
outputs will be set to logic state that were setup
at the D inputs.
2
MOStechnology.
74ACT574
OCTAL D-TYPE FLIP FLOP
DIP
ORDER CODES
PACKAGETUBET & R
DIPM74ACT574B
SOPM74ACT574MM74ACT574MTR
TSSOPM74ACT574TTR
While the (OE) input is low, the 8 outputs will be
in a normal logic state (high or low logic level)
and while high level the outputs will be in a high
impedancestate.
The output control does not affect the internal
operation of flip flop; that is, the old data can be
retained or the new data can be entered even
whilethe outputsare off.
The device is designed to interface directly High
Speed CMOS system with TTL and NMOS
components.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
1)CPDisdefinedasthevalue oftheIC’sinternal equivalentcapacitance whichiscalculated fromtheoperating current consumption withoutload.(Referto
TestCircuit).Averageoperatingcurrent canbeobtainedbythefollowingequation.I
(opr)= CPD• VCC• fIN+ICC/n(percircuit)
CC
=25oC-40 to 85oC
A
Min. Typ. Max. Min. Max.
4
pF
5/11
Page 6
74ACT574
TESTCIRCUIT
TESTSWITCH
t
PLH,tPHL
t
PZL,tPLZ
t
PZH,tPHZ
CL= 50 pF orequivalent (includes jig and probe capacitance)
=500Ωorequivalent
R
L=R1
R
ofpulse generator(typically50Ω)
T=ZOUT
Open
2V
CC
Open
WAVEFORM1: PROPAGATION DELAYS, SETUP AND HOLD TIMES (f=1MHz;50% duty cycle)
6/11
Page 7
74ACT574
WAVEFORM2: OUTPUTENABLEAND DISABLETIMES
(f=1MHz;50% duty cycle)
WAVEFORM3: PULSEWIDTH
7/11
Page 8
74ACT574
Plastic DIP-20 (0.25) MECHANICAL DATA
DIM.
MIN.TYP.MAX.MIN.TYP.MAX.
a10.2540.010
B1.391.650.0550.065
b0.450.018
b10.250.010
D25.41.000
E8.50.335
e2.540.100
e322.860.900
F7.10.280
I3.930.155
L3.30.130
Z1.340.053
mminch
8/11
P001J
Page 9
SO-20 MECHANICAL DATA
74ACT574
DIM.
MIN.TYP.MAX.MIN.TYP.MAX.
A2.650.104
a10.100.200.0040.007
a22.450.096
b0.350.490.0130.019
b10.230.320.0090.012
C0.500.020
c145 (typ.)
D12.6013.000.4960.512
E10.0010.650.3930.419
e1.270.050
e311.430.450
F7.407.600.2910.299
L0.501.270.190.050
M0.750.029
S8 (max.)
mminch
P013L
9/11
Page 10
74ACT574
TSSOP20 MECHANICAL DATA
DIM.
mminch
MIN.TYP.MAX.MIN.TYP.MAX.
A1.10.433
A10.050.100.150.0020.0040.006
A20.850.90.950.3350.3540.374
b0.190.300.00750.0118
c0.090.20.00350.0079
D6.46.56.60.2520.2560.260
E6.256.46.50.2460.2520.256
E14.34.44.480.1690.1730.176
e0.65 BSC0.0256 BSC
K0
o
o
4
o
8
o
0
o
4
L0.500.600.700.0200.0240.028
o
8
A
PIN 1 IDENTIFICATION
10/11
A2
A1
b
e
K
c
L
E
D
E1
1
Page 11
74ACT574
Information furnished isbelieved to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject tochange without notice. Thispublication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in lifesupport devices or systems withoutexpress written approval of STMicroelectronics.
The ST logo is a registeredtrademark of STMicroelectronics
2000 STMicroelectronics – Printed in Italy – All RightsReserved
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.
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