Datasheet 74ACT520SC, 74ACT520PC, 74ACT520CW, 74ACT520SJX, 74ACT520SJ Datasheet (Fairchild Semiconductor)

© 1999 Fairchild Semiconductor Corporation DS010194 www.fairchildsemi.com

February 1989
Revised November 1999

74AC520 • 74ACT520 8-Bit Identity Comparator

74AC520 • 74ACT520
8-Bit Identity Comparator

General Description

The AC/ACT520 are exp andable 8-bit compara tors. They
compare two words of up to e ight bits each an d provide a
LOW output when the two words match bit for bit. The
expansion input I

A = B

also serves as an active LOW enable

input.

Features

■ Compares two 8-bit words in 6.5 ns typ

■ Expandable to any word length

■ 20-pin package

■ Outputs source/sink 24 mA

■ ACT520 has TTL-compatible inputs

Ordering Code:

Device also available in Tape and Reel. Specify by appending s uffix let te r “X” to the ordering code.

Logic Symbols

IEEE/IEC

Connection Diagram

Pin Descriptions

FACT is a trademark of Fairchild Semiconductor Corporation.

Order Number Package Number Package Description

74AC520SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74AC520PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
74ACT520SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ACT520SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT520PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Pin Names Description

A

0–A7

Word A Inputs

B

0–B7

Word B Inputs

T

A = B

Expansion or Enable Input

O

A = B

Identity Output

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74AC520 • 74ACT520

Truth Table

H = HIGH Voltage Level
L = LOW Voltage Level

Note 1: *A

0

= B0, A1 = B1, A2 = B2, etc.

Logic Diagram

Please note that this diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation delays.

Applications

Ripple Expansion

Parallel Expansion

Inputs Outputs

I

A = B

A, B O

A = B

LA = B (Note 1) L

LA ≠ Β H
HA = B (Note 1) H
HA ≠ Β H

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74AC520 • 74ACT520

Absolute Maximum Ratings(Note 2) Recommended Operating

Conditions

Note 2: Absolute max imum ratings are those values beyond w hich damage

to the device may occu r. The databook spe cificatio ns shou ld be met, wit h­out exception, to ensure that the system de sign is relia ble over its p ower
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specif ic at ions.

DC Electrical Characteristics for AC

Note 3: All outputs loaded; thres holds on input associate d w it h output under test.
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
Note 5: I

IN

and ICC @ 3.0V are guaranteed to be less than or equa l t o th e respective limit @ 5.5V VCC.

Supply Voltage (VCC) −0.5V to +7.0V
DC Input Diode Current (I

IK

)

V

I

= −0.5V −20 mA

V

I

= VCC + 0.5V +20 mA

DC Input Voltage (V

I

) −0.5V to VCC + 0.5V

DC Output Diode Current (I

OK

)

V

O

= −0.5V −20 mA

V

O

= VCC + 0.5V +20 mA

DC Output Voltage (V

O

) −0.5V to VCC + 0.5V

DC Output S ource

or Sink Current (I

O

) ±50 mA

DC V

CC

or Ground Current

per Output Pin (I

CC

or I

GND

) ±50 mA

Storage Temperature (T

STG

) −65°C to +150°C

Junction Temperature (T

J

)

PDIP 140°C

Supply Voltage (V

CC

)
AC 2.0V to 6.0V
ACT 4.5V to 5.5V
Input Voltage (V

I

)0V to V

CC

Output Voltage (VO)0V to V

CC

Operating Temperature (TA) −40°C to +85°C
Minimum Input Edge Rate (∆V/∆t)

AC Devices

V

IN

from 30% to 70% of V

CC

VCC @ 3.3V, 4.5V, 5.5V 125 mV/ns

Minimum Input Edge Rate (∆V/∆t)

ACT Devices
V

IN

from 0.8V to 2.0V

V

CC

@ 4.5V, 5.5V 125 mV/ns

Symbol Parameter

V

CC

TA = +25°C TA = −40°C to +85°C

Units Conditions

(V) Typ Guaranteed Limits

V

IH

Minimum HIGH Level 3.0 1.5 2.1 2.1 V

OUT

= 0.1V

Input Voltage 4.5 2.25 3.15 3.15 V or VCC − 0.1V

5.5 2.75 3.85 3.85

V

IL

Maximum LOW Level 3.0 1.5 0.9 0.9 V

OUT

= 0.1V

Input Voltage 4.5 2.25 1.35 1.35 V or VCC − 0.1V

5.5 2.75 1.65 1.65

V

OH

Minimum HIGH Level 3.0 2.99 2.9 2.9
Output Voltage 4.5 4.49 4.4 4.4 V I

OUT

= −50 µA

5.55.495.4 5.4
VIN = VIL or V

IH

3.0 2.56 2.46 IOH = −12 mA

4.5 3.86 3.76 V I

OH

= −24 mA

5.5 4.86 4.76 I

OH

= −24 mA (Note 3)

V

OL

Maximum LOW Level 3.0 0.002 0.1 0.1
Output Voltage 4.5 0.001 0.1 0.1 V I

OUT

= 50 µA

5.5 0.001 0.1 0.1
VIN = VIL or V

IH

3.0 0.36 0.44 IOL = 12 mA

4.5 0.36 0.44 V IOL = 24 mA

5.5 0.36 0.44 IOL = 24 mA (Note 3)

I

IN

(Note 5) Maximum Input Leakage Current 5.5 ±0.1 ±1.0 µAVI = VCC, GND, A Inputs Only

I

IH

Maximum Input HIGH Leakage Current 5.5 10.0 10.0 µAVI = VCC, B Inputs Only

I

IL

Maximum Input LOW Leakage Current 5.5 −0.3 −0.6 −1.0 mA VI = VCC, B Inputs Only

I

OLD

Minimum Dynamic 5.5 75 mA V

OLD

= 1.65V Max

I

OHD

Output Current (Note4) 5.5 −75 mA V

OHD

= 3.85V Min

I

CC

Maximum Quiescent Supply Current 5.5 4.0 40.0 µAVIN = V

CC

I

CC

(Note 5) Maximum Quiescent Supply Current 5.5 2.3 4.8 8.0 mA VIN = GND

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74AC520 • 74ACT520

DC Electrical Characteristics for ACT

Note 6: All outputs loaded; thresholds on input assoc iat ed with output under tes t.
Note 7: Maximum test duratio n 2. 0 ms, one output loaded at a time.

Symbol Parameter

V

CC

TA = +25°C TA = −40°C to +85°C

Units Conditions

(V) Typ Guaranteed Limits

V

IH

Minimum HIGH Level 4.5 1.5 2.0 2.0

V

V

OUT

= 0.1V

Input Voltage 5.5 1.5 2.0 2.0 or VCC − 0.1V

V

IL

Maximum LOW Level 4.5 1.5 0.8 0.8

V

V

OUT

= 0.1V

Input Voltage 5.5 1.5 0.8 0.8 or V

CC

− 0.1V

V

OH

Minimum HIGH Level 4.5 4.49 4.4 4.4

VI

OUT

= −50 µA

Output Voltage 5.5 5.49 5.4 5.4

VIN = VIL or V

IH

4.5 3.86 3.76 V IOH = −24 mA

5.5 4.86 4.76 I

OH

= −24 mA (Note 6)

V

OL

Maximum LOW Level 4.5 0.001 0.1 0.1

VI

OUT

= 50 µA

Output Voltage 5.5 0.001 0.1 0.1

VIN = VIL or V

IH

4.5 0.36 0.44 V IOL = 24 mA

5.5 0.36 0.44 IOL = 24 mA (Note 6)

I

IN

Maximum Input

5.5 ±0.1 ±1.0 µAVI = VCC, GND

Leakage Current

I

IH

Maximum Input

5.5 10.0 10.0 µA

VI = V

CC

HIGH Leakage Current B Inputs Only

I

IL

Maximum Input

5.5 −0.3 −0.6 −1.0 mA

VI = V

CC

LOW Leakage Current B Inputs Only

I

CCT

Maximum

5.5 0.6 1.5 mA VI = VCC − 2.1V

ICC/Input

I

OLD

Minimum Dynamic 5.5 75 mA V

OLD

= 1.65V Max

I

OHD

Output Current (Note7) 5.5 −75 mA V

OHD

= 3.85V Min

I

CC

Maximum Quiescent

5.5 4.0 40.0 µA

VIN = V

CC

Supply Current or GND

I

CC

Maximum Quiescent

5.5 2.3 4.8 8.0 mA VIN = GND

Supply Current

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74AC520 • 74ACT520

AC Electrical Characteristics for AC

Note 8: Voltage Range 3.3 is 3.3V ± 0.3V

Voltage Range 5.0 is 5.0V ± 0.5V

AC Electrical Characteristics for ACT

Note 9: Voltage Range 5.0 is 5.0V ± 0.5V

Capacitance

V

CC

TA = +25°CT

A

= −40°C to +85°C

Symbol Parameter (V)

C

L

= 50 pF CL = 50 pF

Units

(Note 8) Min Typ Max Min Max

t

PLH

Propagation Delay 3.3 4.0 7.5 11.5 3.0 13.0

ns

A

n

or Bn to O

A = B

5.0 2.5 5.5 8.5 2.0 9.5

t

PHL

Propagation Delay 3.3 4.5 8.0 12.0 3.5 13.5

ns

A

n

or Bn to O

A = B

5.0 3.0 5.5 9.0 2.5 10.0

t

PLH

Propagation Delay 3.3 3.5 5.5 8.5 2.5 9.5

ns

I

A = B

to O

A = B

5.0 2.5 4.5 6.5 2.0 7.0

t

PHL

Propagation Delay 3.3 3.5 5.5 8.5 2.5 9.5

ns

I

A = B

to O

A = B

5.0 2.5 4.5 6.5 2.0 7.0

V

CC

TA = +25°CT

A

= −40°C to +85°C

Symbol Parameter (V)

C

L

= 50 pF CL = 50 pF

Units

(Note 9) Min Typ Max Min Max

t

PLH

Propagation Delay

5.0 3.0 5.5 8.5 2.5 9.5 ns

An or Bn to O

A = B

t

PHL

Propagation Delay

5.0 3.0 6.0 10.0 2.5 11.5 ns

An or Bn to O

A = B

t

PLH

Propagation Delay

5.0 2.0 4.0 6.0 2.0 6.5 ns

I

A = B

to O

A = B

t

PHL

Propagation Delay

5.0 2.5 5.0 7.5 2.0 8.5 ns

I

A = B

to O

A = B

Symbol Parameter Typ Units Conditions

C

IN

Input Capacitance 4.5 pF VCC = OPEN

C

PD

Power Dissipation Capacitance 40 pF VCC = 5.0V

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74AC520 • 74ACT520

Physical Dimensions inches (millimeters) unless otherwise noted

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body

Package Number M20B

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74AC520 • 74ACT520

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M20D

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74AC520 • 74ACT520 8-Bit Identity Comparator

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Package Number N20A

Fairchild does not assume any responsibility for use of any circuitr y described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea­sonably expected to result in a significant inju ry to the
user.

2. A critical component i n any compon ent of a lif e supp ort
device or system whose failure t o perform can be rea­sonably expected to ca use the failure of the life supp ort
device or system, or to affect its safety or effectiveness.

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