Datasheet 74ACT174 Datasheet (Fairchild)

74AC174 • 74ACT174 Hex D-Type Flip-Flop with Master Reset

November 1988 Revised October 2000

General Description

The AC/ACT174 is a high-sp eed hex D-type flip-flo p. The device is used pr imarily as a 6-bit edge-triggered storage register. The information on the D inp uts is transferred to storage during the LOW-to-HIGH clock transition. The device has a Master Reset t o simultaneousl y clear all flipflops.

Features

■ ICC reduced by 50%

■ Outputs source/sink 24 mA

■ ACT174 has TTL-compatible inputs

Ordering Code:

Order Number Package Number Package Description

74AC174SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74AC174SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74AC174MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74AC174PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 74ACT174SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74ACT174SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ACT174MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74ACT174PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the or dering code.

Logic Symbols

Connection Diagram

IEEE/IEC

Pin Descriptions

Pin Names Description

D

0–D5

CP Clock Pulse Input MR Master Reset Input Q

0–Q5

FACT is a trademark of Fairchild Semiconductor Corporation.

Data Inputs

Outputs

Functional Description

The AC/ACT174 consists o f six edge-t riggered D-t ype flipflops with individual D inputs and Q outputs. The Clock (CP) and Master Reset (MR Each D input’s state is transferred to the corresponding flipflop’s output following the LOW-to-HIGH Clock (CP) transition. A LOW input to th e Master Reset (MR outputs LOW independent of Clock or Data inputs. The AC/ ACT174 is useful for applications where the true output only is required an d the Clock and Master Reset are com mon to all storage elements.

74AC174 • 74ACT174

) are common to all flip-flops.

) will force all

Truth Table

Inputs Output

MR

LX X L H H HL X Q

H = HIGH Voltage Level L = LOW Voltage Level



= LOW-to-HIGH Transition

X = Immaterial

CP D Q

 

HH LL

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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Absolute Maximum Ratings(Note 1) Recommended Operating

Supply Voltage (VCC) −0.5V to +7.0V DC Input Diode Current (I

V

= −0.5V −20 mA

I

= VCC + 0.5V +20 mA

V

I

DC Input Voltage (V DC Output Diode Current (I

= −0.5V −20 mA

V

O

V

= V

+ 0.5V +20 mA

CC

DC Output Voltage (V

)

IK

) −0.5V to VCC + 0.5V

I

)

OK

) −0.5V to V

O

CC

+ 0.5V

DC Output Source

or Sink Current (I

DC V

or Ground Current

CC

per Output Pin (I Storage Temperature (T Junction Temperature (T

PDIP 140

) ±50 mA

O

or I

CC

) ±50 mA

GND

) −65°C to +150°C

STG

)

J

°C

Conditions

Supply Voltage (V AC 2.0V to 6.0V ACT 4.5V to 5.5V Input Voltage (V Output Voltage (VO)0V to V Operating Temperature (TA) −40°C to +85°C Minimum Input Edge Rate (

AC Devices V

from 30% to 70% of V

IN

VCC @ 3.3V, 4.5V, 5.5V 125 mV/ns

Minimum Input Edge Rate (

ACT Devices V

from 0.8V to 2.0V

IN

@ 4.5V, 5.5V 125 mV/ns

V

CC

Note 1: Absolute max imum ratings are those va lues beyond which damage to the device may occu r. The databook spe cificatio ns shou ld be met, w ithout exception, to ensure that the system de sign is relia ble over its p ower supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specif ic at ions.

)

CC

)0V to V

I

∆V/∆t)

CC

∆V/∆t)

DC Electrical Characteristics for AC

V

Symbol Parameter

V

IL

V

OL

I

IN

(Note 4) Leakage Current or GND I

OLD

I

OHD

I

CC

(Note 4) Supply Current or GND

Note 2: All outputs loaded; thres holds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: I

Minimum HIGH Level 3.0 1.5 2.1 2.1 V

IH

Input Voltage 4.5 2.25 3.15 3.15 V or VCC − 0.1V

Maximum LOW Level 3.0 1.5 0.9 0.9 V Input Voltage 4.5 2.25 1.35 1.35 V or VCC − 0.1V

Minimum HIGH Level 3.0 2.99 2.9 2.9

OH

Output Voltage 4.5 4.49 4.4 4.4 V I

Maximum LOW Level 3.0 0.002 0.1 0.1 Output Voltage 4.5 0.001 0.1 0.1 V I

Maximum Input

Minimum Dynamic 5.5 75 mA V Output Current (Note 3) 5.5 −75 mA V Maximum Quiescent

and ICC @ 3.0V are guaranteed to be less than or e qual to the respective lim it @ 5. 5V VCC.

IN

CC

(V) Typ Guaranteed Limits

5.5 2.75 3.85 3.85

5.5 2.75 1.65 1.65

5.5 5.49 5.4 5.4

3.0 2.56 2.46 IOH = −12 mA

4.5 3.86 3.76 V I

5.5 4.86 4.76 I

5.5 0.001 0.1 0.1

3.0 0.36 0.44 IOL = 12 mA

4.5 0.36 0.44 V IOL = 24 mA

5.5 0.36 0.44 IOL = 24 mA (Note 2)

5.5 ±0.1 ±1.0 µA

5.5 4.0 40.0 µA

TA = +25°C TA = −40°C to +85°C

Units Conditions

OUT

= −50 µA

OUT

VIN = VIL or V

= −24 mA

OH

= −24 mA (Note 2)

OH

= 50 µA

OUT

VIN = VIL or V

VI = V

OLD OHD

VIN = V

74AC174 • 74ACT174

CC CC

= 0.1V

IH

CC

= 1.65V Max = 3.85V Min

CC

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DC Electrical Characteristics for ACT

V

Symbol Parameter

V

IH

Minimum HIGH Level 4.5 1.5 2.0 2.0

CC

(V) Typ Guaranteed Limits

Input Voltage 5.5 1.5 2.0 2.0 or VCC − 0.1V

V

IL

Maximum LOW Level 4.5 1.5 0.8 0.8 Input Voltage 5.5 1.5 0.8 0.8 or V

V

OH

74AC174 • 74ACT174

Minimum HIGH Level 4.5 4.49 4.4 4.4 Output Voltage 5.5 5.49 5.4 5.4

4.5 3.86 3.76 V IOH = −24 mA

5.5 4.86 4.76 I

V

OL

Maximum LOW Level 4.5 0.001 0.1 0.1 Output Voltage 5.5 0.001 0.1 0.1

4.5 0.36 0.44 V IOL = 24 mA

5.5 0.36 0.44 IOL = 24 mA (Note 5)

I

IN

I

CCT

I

OLD

I

OHD

I

CC

Note 5: All outputs loaded; thresholds on input associated with output under test. Note 6: Maximum test dura tio n 2. 0 ms, one output loaded at a time.

Maximum Input Leakage Current Maximum ICC/Input

5.5 ±0.1 ±1.0 µAVI = VCC, GND

5.5 0.6 1.5 mA VI = VCC − 2.1V

Minimum Dynamic 5.5 75 mA V Output Current (Note 6) 5.5 −75 mA V Maximum Quiescent Supply Current or GND

5.5 4.0 40.0 µA

AC Electrical Characteristics for AC

V

Symbol Parameter

f

MAX

Maximum Clock 3.3 90 100 70 Frequency 5.0 100 125 100

t

PLH

t

PHL

t

PHL

Note 7: Voltage Range 3.3 is 3.3V ± 0.3V

Propagation Delay 3.3 2.0 9.0 11.5 1.5 12.5 CP to Q

n

Propagation Delay 3.3 2.0 8.5 11.0 1.5 12.0 CP to Q

n

Propagation Delay 3.3 2.5 9.0 11.5 2.0 12.5 MR to Q

n

Voltage Range 5.0 is 5.0V ± 0.5V

CC

(V)

(Note 7)

5.0 1.5 6.0 8.5 1.0 9.5

5.0 1.5 6.0 8.0 1.0 9.0

5.0 1.5 7.0 9.0 1.5 10.5

TA = +25°CT

= −40°C to +85°C

A

TA = +25°C C

= 50 pF

L

T

Min Typ Max Min Max

Units Conditions

V

= 0.1V

OUT

V

= 0.1V

OUT

V

VI

CC

OUT

− 0.1V

= −50 µA

VIN = VIL or V

= −24 mA (Note 5)

OH

VI

= −40°C to +85°C

A

C

= 50 pF

L

= 50 µA

OUT

VIN = V

OLD OHD

VIN = V

or V

IL

= 1.65V Max = 3.85V Min

CC

IH

Units

MHz

ns

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AC Operating Requirements for AC

V

Symbol Par ameter

t

S

t

H

t

W

Setup Time, HIGH or LOW 3.3 2.5 6.5 7.0

to CP 5.0 2.0 5.0 5.5

D

n

Hold Time, HIGH or LOW 3.3 1.0 3.0 3.0 D

to CP 5.0 0.5 3.0 3.0

n

MR Pulse Width, LOW 3.3 1.0 5.5 7.0

CC

(V)

(Note 8)

5.0 1.0 5.0 5.0

t

W

CP Pulse Width 3.3 1.0 5.5 7.0

5.0 1.0 5.0 5.0

t

REC

Recovery Time 3.3 0 2.5 2.5 MR to CP 5.0 0 2.0 2.0

Note 8: Voltage Range 3.3 is 3.3V ± 0.3V

Voltage Range 5.0 is 5.0V ± 0.5V

AC Electrical Characteristics for ACT

V

Symbol Parameter

f

MAX

Maximum Clock Frequency

t

PLH

t

PHL

t

PHL

Note 9: Voltage Range 5.0 is 5.0V ± 0.5V

Propagation Delay CP to Q

n

Propagation Delay CP to Q

n

Propagation Delay MR

to Q

n

CC

(V)

(Note 9)

5.0 165 200 140 MHz

5.0 1.5 7.0 10.5 1.5 11.5 ns

5.0 1.5 6.5 9.5 1.5 11.0 ns

= +25°C

T

A

C

= 50 pF

L

= −40°C to +85°C

T

A

C

= 50 pF

L

Typ Guaranteed Minimum

TA = +25°C CL = 50 pF

TA = −40°C to +85°C

CL = 50 pF

Min Typ Max Min Max

74AC174 • 74ACT174

Units

ns

Units

AC Operating Requirements for ACT

Symbol Parameter

t

S

t

H

Setup Time, HIGH or LOW

to CP

D

n

Hold Time, HIGH or LOW Dn to CP

t

W

t

W

t

rec

MR Pulse Width, LOW 5.0 1.5 3.0 3.5 ns CP Pulse Width, HIGH or LOW 5.0 1.5 3.0 3.5 ns Recovery Time MR to CP

Note 10: Voltage Ran ge 5.0 is 5.0V ± 0.5V

T

= +25°C

V

CC

(V)

(Note 10)

A

= 50 pF

C

L

Typ Guaranteed Minimum

5.0 0.5 1.5 1.5 ns

5.0 1.0 2.0 2.0 ns

5.0 −1.0 0.5 0.5 ns

T

= −40°C to +85°C

A

= 50 pF

C

L

Capacitance

Symbol Parameter Typ Units Conditions

C

IN

C

PD

Input Capacitance 4.5 pF VCC = OPEN Power Dissipation Capacitance 85.0 pF VCC = 5.0V

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Units

Physical Dimensions inches (millimeters) unless otherwise noted

74AC174 • 74ACT174

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

Package Number M16A

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

74AC174 • 74ACT174

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M16D

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

74AC174 • 74ACT174

16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

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Package Number MTC16

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

74AC174 • 74ACT174 Hex D-Type Flip-Flop with Master Reset

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Fairchild does not assume any responsibility for use of any circuitry described , no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

1. Life support de vices o r syst ems are dev ic es or syste ms which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provide d in the l abe ling, can be reasonably expected to result in a significant injury to the user.

Package Number N16E

2. A critica l compo nent i n any compo nent o f a l ife supp ort device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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