Page 1
54ACT16841, 74ACT16841
20-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCAS174A – MAY 1991 – REVISED APRIL 1996
D
Members of the Texas Instruments
Widebus
D
Inputs Are TTL-Voltage Compatible
D
3-State Outputs Drive Bus Lines Directly
D
Provide Extra Bus Driving/Latches
Family
Necessary for Wider Address/Data Paths or
Buses With Parity
D
Flow-Through Architecture Optimizes
PCB Layout
D
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D
EPIC
(Enhanced-Performance Implanted
CMOS) 1-µm Process
D
500-mA Typical Latch-Up Immunity at
125°C
D
Package Options Include Plastic Thin
Shrink Small-Outline (DGG) Packages,
300-mil Shrink Small-Outline (DL) Packages
Using 25-mil Center-to-Center Pin
Spacings, and 380-mil Fine-Pitch Ceramic
Flat (WD) Packages Using 25-mil
Center-to-Center Pin Spacings
description
These 20-bit latches feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
54ACT16841 . . . WD PACKAGE
74ACT16841 . . . DGG OR DL PACKAGE
1OE
1Q1
1Q2
GND
1Q3
1Q4
V
CC
1Q5
1Q6
1Q7
GND
1Q8
1Q9
1Q10
2Q1
2Q2
2Q3
GND
2Q4
2Q5
2Q6
V
CC
2Q7
2Q8
GND
2Q9
2Q10
2OE
(TOP VIEW)
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
1LE
1D1
1D2
GND
1D3
1D4
V
CC
1D5
1D6
1D7
GND
1D8
1D9
1D10
2D1
2D2
2D3
GND
2D4
2D5
2D6
V
CC
2D7
2D8
GND
2D9
2D10
2LE
The ’ACT16841 can be used as two 10-bit latches
or one 20-bit latch. The 20 latches are transparent
D-type. While the latch-enable (1LE or 2LE) input
is high, the Q outputs of the corresponding 10-bit
latch follow the data (D) inputs. When LE is taken
low, the Q outputs are latched at the levels that
were set up at the D inputs.
A buffered output-enable (1OE
or 2OE) input can be used to place the outputs of the corresponding 10-bit latch
in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state,
the outputs neither load nor drive the bus lines significantly.
OE does not affect the internal operation of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1996, Texas Instruments Incorporated
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54ACT16841, 74ACT16841
20-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCAS174A – MAY 1991 – REVISED APRIL 1996
description (continued)
The 74ACT16841 is packaged in TI’s shrink small-outline package (DL), which provides twice the I/O pin count
and functionality of standard small-outline packages in the same printed-circuit-board area.
The 54ACT16841 is characterized for operation over the full military temperature range of –55°C to 125°C. The
74ACT16841 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each 10-bit latch)
INPUTS
OE LE D
L H H H
L HL L
L LX Q
H X X Z
OUTPUT
Q
0
logic symbol
†
1OE
1LE
2OE
2LE
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
1D9
1D10
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
2D9
2D10
1
56
28
29
55
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
30
EN2
C1
EN4
C3
1D
3D
2
10
12
13
14
15
16
17
19
20
21
23
24
26
27
1Q1
3
1Q2
5
1Q3
6
1Q4
8
1Q5
9
1Q6
1Q7
1Q8
1Q9
1Q10
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
2Q9
2Q10
2
4
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 3
UNIT
logic diagram (positive logic)
54ACT16841, 74ACT16841
20-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCAS174A – MAY 1991 – REVISED APRIL 1996
1OE
1LE
1D1
1
56
55
C1
1D
To Nine Other Channels
2
1Q1
2OE
2LE
2D1
28
29
42
C1
1D
To Nine Other Channels
15
2Q1
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
Input clamp current, IIK (VI < 0 or VI > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±500 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum package power dissipation at T
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils.
(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
= 55°C (in still air) (see Note 2): DGG package 1 W. . . . . . . . . .
A
DL package 1.4 W. . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
†
recommended operating conditions (see Note 3)
54ACT16841 74ACT16841
MIN NOM MAX MIN NOM MAX
V
V
V
V
V
I
OH
I
OL
∆t/∆v Input transition rise or fall rate 0 10 0 10 ns/V
T
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
Supply voltage 4.5 5 5.5 4.5 5 5.5 V
CC
High-level input voltage 2 2 V
IH
Low-level input voltage 0.8 0.8 V
IL
Input voltage 0 V
I
Output voltage 0 V
O
High-level output current –24 –24 mA
Low-level output current 24 24 mA
Operating free-air temperature –55 125 –40 85 °C
A
CC
CC
0 V
0 V
CC
CC
V
V
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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54ACT16841, 74ACT16841
PARAMETER
TEST CONDITIONS
V
UNIT
I
A
I
mA
I
50 µA
I
24 mA
UNIT
thHold time, data after LE↓
ns
PARAMETER
UNIT
D
Q
ns
LE
Q
ns
OE
Q
ns
OE
Q
ns
20-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCAS174A – MAY 1991 – REVISED APRIL 1996
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
CC
=–50 µ
OH
V
OH
V
OL
I
I
I
OZ
I
CC
‡
∆I
CC
C
i
C
†
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
‡
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
o
= –24
OH
IOH = –75 mA
=
OL
=
OL
IOL = 75 mA
VI = VCC or GND 5.5 V ±0.1 ±1 ±1 µA
VO = VCC or GND 5.5 V ±0.5 ±5 ±5 µA
VI = VCC or GND, IO = 0 5.5 V 8 80 80 µA
One input at 3.4 V ,
Other inputs at VCC or GND
VI = VCC or GND 5 V 3 pF
VO = VCC or GND 5 V 11 pF
†
†
4.5 V 4.4 4.4 4.4
5.5 V 5.4 5.4 5.4
4.5 V 3.94 3.8 3.8
5.5 V 4.94 4.8 4.8
5.5 V 3.85 3.85
4.5 V 0.1 0.1 0.1
5.5 V 0.1 0.1 0.1
4.5 V 0.36 0.44 0.44
5.5 V 0.36 0.44 0.44
5.5 V 1.65 1.65
5.5 V 0.9 1 1 mA
TA = 25°C 54ACT16841 74ACT16841
MIN TYP MAX MIN MAX MIN MAX
V
V
timing requirements over recommended operating free-air temperature range,
V
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
CC
TA = 25°C 54ACT16841 74ACT16841
MIN MAX MIN MAX MIN MAX
t
w
t
su
Pulse duration, LE high 4 4 4 ns
Setup time, data before LE↓ 1.5 1.5 1.5 ns
High 3 3 3
Low 4.5 4.5 4.5
switching characteristics over recommended operating free-air temperature range,
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
V
CC
TA = 25°C 54ACT16841 74ACT16841
MIN TYP MAX MIN MAX MIN MAX
4 7.1 10.3 4 11.8 4 11.8
3.2 6.9 11 3.2 12.2 3.2 12.2
4.5 7.7 11.3 4.5 12.7 4.5 12.7
4.3 7.8 11.4 4.3 12.7 4.3 12.7
3.1 6.4 10.1 3.1 11.3 3.1 11.3
3.8 7.6 12.1 3.8 13.7 3.8 13.7
4 7.3 9.5 4 10.2 4 10.2
4 6.8 8.9 4 9.6 4 9.6
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
FROM TO
(INPUT) (OUTPUT)
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 5
CpdPower dissipation capacitance
C
f
pF
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
p
From Output
Under Test
CL = 50 pF
(see Note A)
p
PARAMETER MEASUREMENT INFORMATION
2 × V
CC
500 Ω
500 Ω
S1
Open
GND
54ACT16841, 74ACT16841
20-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCAS174A – MAY 1991 – REVISED APRIL 1996
Outputs enabled
Outputs disabled
p
= 50 pF,
L
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
= 1 MHz
Open
2 × V
CC
GND
41
10
p
LOAD CIRCUIT
t
w
Input
In-Phase
Output
Out-of-Phase
NOTES: A. CL includes probe and jig capacitance.
1.5 V 1.5 V
VOLTAGE WAVEFORMS
Input
t
PLH
t
PHL
Output
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
1.5 V 1.5 V
50% V
CC
50% V
CC
VOLTAGE WAVEFORMS
t
PHL
50% V
t
PLH
50% V
3 V
0 V
CC
CC
3 V
0 V
V
V
V
V
OH
OL
OH
OL
Timing Input
(see Note B)
Data Input
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
CC
t
PZL
t
PZH
t
su
1.5 V
VOLTAGE WAVEFORMS
1.5 V
t
PLZ
50% V
t
PHZ
50% V
VOLTAGE WAVEFORMS
1.5 V
CC
CC
t
h
1.5 V
1.5 V
20% V
80% V
CC
CC
3 V
0 V
3 V
0 V
3 V
0 V
[
V
V
[
V
OL
OH
0 V
CC
Figure 1. Load Circuit and Voltage Waveforms
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IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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