Page 1
SN54ACT16651, 74ACT16651
16-BIT TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS449A – FEBRUARY 1993 – REVISED APRIL 1996
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Members of the Texas Instruments
Widebus
Family
D
Inputs Are TTL-Voltage Compatible
D
Inverting Data Paths
D
Independent Registers and Enables for
A and B Buses
D
Multiplexed Real-Time and Stored Data
D
Flow-Through Architecture Optimizes
PCB Layout
D
Distributed VCC and GND Pin
Configurations Minimize High-Speed
Switching Noise
D
EPIC
(Enhanced-Performance Implanted
CMOS) 1-µm Process
D
500-mA Typical Latch-Up Immunity at
125°C
D
Packaged in Plastic 300-mil Shrink
Small-Outline (DL) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Packages
Using 25-mil Center-to-Center Pin Spacings
description
The SN54ACT16651 and 74ACT16651 are 16-bit
bus transceivers that consist of D-type flip-flops
and control circuitry arranged for multiplexed
transmission of data directly from the data bus or
from the internal storage registers. These devices
can be used as two 8-bit transceivers or one 16-bit
transceiver.
Complementary output-enable (OEAB and
OEBA
) inputs are provided to control the
transceiver functions. Select-control (SAB and
SBA) inputs are provided to select whether
real-time or stored data is transferred. A low input
level selects real-time data, and a high input level
selects stored data. The circuitry used for select
control eliminates the typical decoding glitch that
occurs in a multiplexer during the transition
between stored and real-time data. Figure 1
illustrates the four fundamental bus-management
functions that can be performed with the
SN54ACT16651 and 74ACT16651.
Copyright 1996, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1OEAB
1CLKAB
1SAB
GND
1A1
1A2
V
CC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
V
CC
2A7
2A8
GND
2SAB
2CLKAB
2OEAB
1OEBA
1CLKBA
1SBA
GND
1B1
1B2
V
CC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
V
CC
2B7
2B8
GND
2SBA
2CLKBA
2OEBA
SN54ACT16651 . . . WD PACKAGE
74ACT16651 . . . DL PACKAGE
(TOP VIEW)
Page 2
SN54ACT16651, 74ACT16651
16-BIT TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS449A – FEBRUARY 1993 – REVISED APRIL 1996
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
Data on the A or B bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the
appropriate clock (CLKAB or CLKBA) inputs regardless of the levels on the select-control or output-enable
inputs. When SAB and SBA are in the real-time transfer mode, it is also possible to store data without using the
internal D-type flip-flops by simultaneously enabling OEAB and OEBA. In this configuration, each output
reinforces its input. Thus, when all other data sources to the two sets of bus lines are at high impedance, each
set of bus lines remains at its last state.
The 74ACT16651 is packaged in TI’s shrink small-outline package, which provides twice the I/O pin count and
functionality of standard small-outline packages in the same printed-circuit-board area.
The SN54ACT16651 is characterized for operation over the full military temperature range of –55°C to 125°C.
The 74ACT16651 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
DATA I/O
†
OEAB OEBA
CLKAB
CLKBA SAB SBA A1–A8 B1–B8
OPERATION OR FUNCTION
L H L L X X Input Input Isolation
L H ↑↑X X Input Input Store A and B data
X H ↑ L X X Input Unspecified
‡
Store A, hold B
H H ↑↑X
‡
X Input Output Store A in both registers
L X L ↑ X X Unspecified
‡
Input Hold A, store B
L L ↑↑XX‡Output Input Store B in both registers
L L X X X L Output Input Real-time B data to A bus
L L X L X H Output Input Stored B data to A bus
H H X X L X Input Output Real-time A data to B bus
H H L X H X Input Output Stored A data to B bus
H L L L H H Output Output
Stored A data to B bus and
stored B
data to A bus
†
The data-output functions may be enabled or disabled by a variety of level combinations at OEAB or OEBA
. Data-input functions are always
enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs.
‡
Select control = L; clocks can occur simultaneously.
Select control = H; clocks must be staggered to load both registers.
Page 3
SN54ACT16651, 74ACT16651
16-BIT TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS449A – FEBRUARY 1993 – REVISED APRIL 1996
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
REAL-TIME TRANSFER
BUS B TO BUS A
REAL-TIME TRANSFER
BUS A TO BUS B
STORAGE FROM
A, B, OR A AND B
TRANSFER STORED DATA
TO A AND/OR B
BUS B
BUS A
BUS B
BUS A
BUS B
BUS A
BUS B
BUS A
OEAB
X
L
L
OEAB
LL
CLKABXCLKBAXSABXSBA
L
CLKABXCLKBAXSABLSBA
X
H
CLKAB CLKBAXSABXSBA
X
CLKAB CLKBA SAB SBA
X
H
XX
X
X
X
HL L HH
↑
↑
↑↑
OEBA
OEBA
HH
OEAB OEBA
OEAB OEBA
L
Figure 1. Bus-Management Functions
Page 4
SN54ACT16651, 74ACT16651
16-BIT TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS449A – FEBRUARY 1993 – REVISED APRIL 1996
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
C3
EN7 [BA]
29
G12
26
2SAB
5
1A1
1A2
6
1A3
8
1A4
9
1A5
10
1A6
12
1A7
13
1A8
14
1B6
45
1B7
44
1B8
43
1B2
51
1B3
49
1B4
48
1B5
47
1B1
52
3D
27
2CLKAB
G10
31
2SBA
30
2CLKBA
EN8 [AB]
28
2OEAB
EN1 [BA]
56
G6
3
1SAB
2
1CLKAB
G4
54
1SBA
55
1CLKBA
EN2 [AB]
1
1OEAB
C5
C9
C11
15
2A1
2A2
16
2A3
17
2A4
19
2A5
20
2A6
21
2A7
23
2A8
24
2B6
36
2B7
34
2B8
33
2B2
41
2B3
40
2B4
38
2B5
37
2B1
42
9D
1OEBA
2OEBA
5D
1
≥ 1
≥ 1
2
16
6
441
11D
7
≥ 1
≥ 1
8
112
12
10
10
1
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Page 5
SN54ACT16651, 74ACT16651
16-BIT TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS449A – FEBRUARY 1993 – REVISED APRIL 1996
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
TG
TG
TG
TG
C1
1D
C1
1D
1OEBA
1OEAB
1CLKBA
1SBA
1CLKAB
1SAB
1A1
1B1
To Seven Other Channels
56
1
55
54
2
3
5
52
TG
TG
TG
TG
C1
1D
C1
1D
2OEBA
2OEAB
2CLKBA
2SBA
2CLKAB
2SAB
2A1
2B1
To Seven Other Channels
29
28
30
31
27
26
15
42
Page 6
SN54ACT16651, 74ACT16651
16-BIT TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS449A – FEBRUARY 1993 – REVISED APRIL 1996
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±400 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum package power dissipation at TA = 55°C (in still air) (see Note 2): DL package 1.4 W. . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils.
recommended operating conditions (see Note 3)
SN54ACT16651 74ACT16651
MIN NOM MAX MIN NOM MAX
UNIT
V
CC
Supply voltage 4.5 5 5.5 4.5 5 5.5 V
V
IH
High-level input voltage 2 2 V
V
IL
Low-level input voltage 0.8 0.8 V
V
I
Input voltage 0 V
CC
0 V
CC
V
V
O
Output voltage 0 V
CC
0 V
CC
V
I
OH
High-level output current –24 –24 mA
I
OL
Low-level output current 24 24 mA
∆t/∆v Input transition rise or fall rate 0 10 0 10 ns/V
T
A
Operating free-air temperature –55 125 –40 85 °C
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
Page 7
SN54ACT16651, 74ACT16651
16-BIT TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS449A – FEBRUARY 1993 – REVISED APRIL 1996
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C SN54ACT16651 74ACT16651
PARAMETER
TEST CONDITIONS
V
CC
MIN TYP MAX MIN MAX MIN MAX
UNIT
4.5 V 4.4 4.4 4.4
I
OH
= –50 µ
A
5.5 V 5.4 5.4 5.4
4.5 V 3.94 3.7 3.8
VOHI
OH
= –24
mA
5.5 V 4.94 4.7 4.8
V
IOH = –50 mA
†
5.5 V 3.85
IOH = –75 mA
†
5.5 V 3.85
4.5 V 0.1 0.1 0.1
I
OL
= 50 µ
A
5.5 V 0.1 0.1 0.1
4.5 V 0.36 0.5 0.44
VOLI
OL
= 24
mA
5.5 V 0.36 0.5 0.44
V
IOL = 50 mA
†
5.5 V 1.65
IOL = 75 mA
†
5.5 V 1.65
I
I
Control inputs VI = VCC or GND 5.5 V ±0.1 ±1 ±1 µA
I
OZ
‡
A or B ports VO = VCC or GND 5.5 V ±0.5 ±10 ±5 µA
I
CC
VI = VCC or GND, IO = 0 5.5 V 8 160 80 µA
∆I
CC
§
One input at 3.4 V ,
Other inputs at VCC or GND
5.5 V 0.9 1 1 mA
C
i
Control inputs VI = VCC or GND 5 V 4 pF
C
io
A or B ports VO = VCC or GND 5 V 12 pF
†
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
‡
For I/O ports, the parameter IOZ includes the input leakage current.
§
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
timing requirements over recommended operating free-air temperature range,
V
CC
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 2)
TA = 25°C SN54ACT16651 74ACT16651
MIN MAX MIN MAX MIN MAX
UNIT
f
clock
Clock frequency 0 90 0 90 0 90 MHz
t
w
Pulse duration, CLKAB or CLKBA high or low 5.5 5.5 5.5 ns
t
su
Setup time, A before CLKAB↑ or B before CLKBA↑ 5.3 5.3 5.3 ns
t
h
Hold time, A after CLKAB↑ or B after CLKBA↑ 1 1 1 ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
Page 8
SN54ACT16651, 74ACT16651
16-BIT TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS449A – FEBRUARY 1993 – REVISED APRIL 1996
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 2)
FROM TO
TA = 25°C SN54ACT16651 74ACT16651
PARAMETER
(INPUT) (OUTPUT)
MIN TYP MAX MIN MAX MIN MAX
UNIT
f
max
90 90 90 MHz
t
PLH
3 6.6 10 3 12.2 3 11.3
t
PHL
A or B
B or A
4.6 8 10.6 4.6 12.7 4.6 11.9
ns
t
PLH
5.4 9.1 12 5.4 14.8 5.4 13.7
t
PHL
CLKBA or CLKAB
A or B
5.4 9.1 12 5.4 14.6 5.4 13.6
ns
t
PLH
SBA or SAB
4.6 7.9 10.5 4.6 13.1 4.6 12.1
t
PHL
(with A or B high)
A or B
5.4 10.9 15.5 5.4 19.6 5.4 17.8
ns
t
PLH
SBA or SAB
5 10.4 14.9 5 19.2 5 17.3
t
PHL
(with A or B low)
A or B
4.9 8.6 11.9 4.9 13.7 4.9 12.7
ns
t
PZH
3.2 7.2 10.8 3.2 13.6 3.2 12.3
t
PZL
OEBA
A
3.8 8 12.2 3.8 15.3 3.8 13.9
ns
t
PHZ
5.1 7.8 9.8 5.1 11.3 5.1 10.6
t
PLZ
OEBA
A
4.9 7.7 9.9 4.9 11.4 4.9 10.8
ns
t
PZH
4.9 8 10.5 4.9 12.9 4.9 11.9
t
PZL
OEAB
B
5.4 8.8 11.8 5.4 14.7 5.4 13.5
ns
t
PHZ
4.3 7.5 10.7 4.3 12 4.3 11.4
t
PLZ
OEAB
B
4.5 7.6 10.8 4.5 12.3 4.5 11.6
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
p
p
p
Outputs enabled
p
62
p
CpdPower dissipation capacitance per transceiver
Outputs disabled
C
L
=
50 pF
,f = 1 MHz
14
pF
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
Page 9
SN54ACT16651, 74ACT16651
16-BIT TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS449A – FEBRUARY 1993 – REVISED APRIL 1996
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
50% V
CC
1.5 V
1.5 V
1.5 V
3 V
3 V
0 V
0 V
t
h
t
su
VOLTAGE WAVEFORMS
Data Input
t
PLH
t
PHL
t
PHL
t
PLH
V
OH
V
OH
V
OL
V
OL
1.5 V 1.5 V
3 V
0 V
50% V
CC
50% V
CC
Input
Out-of-Phase
Output
In-Phase
Output
Timing Input
50% V
CC
VOLTAGE WAVEFORMS
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
2 × V
CC
500 Ω
500 Ω
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
CC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
V
OL
V
OH
t
PZL
t
PZH
t
PLZ
t
PHZ
1.5 V
1.5 V
≈ V
CC
0 V
50% V
CC
20% V
CC
50% V
CC
80% V
CC
≈ 0 V
3 V
GND
Open
VOLTAGE WAVEFORMS
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open
2 × V
CC
GND
TEST S1
3 V
0 V
1.5 V 1.5 V
t
w
VOLTAGE WAVEFORMS
Input
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 2. Load Circuit and Voltage Waveforms
Page 10
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