Page 1
54ACT16646, 74ACT16646
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS127B – MARCH 1990 – REVISED APRIL 1996
D
Members of the Texas Instruments
Widebus
D
Inputs Are TTL-Voltage Compatible
D
Independent Registers for A and B Buses
D
Multiplexed Real-Time and Stored Data
D
Flow-Through Architecture Optimizes
t
Family
PCB Layout
D
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D
EPIC
t
(Enhanced-Performance Implanted
CMOS) 1-mm Process
D
500-mA Typical Latch-Up Immunity at
125°C
D
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Packages Using
25-mil Center-to-Center Pin Spacings and
380-mil Fine-Pitch Ceramic Flat (WD)
Packages Using 25-mil Center-to-Center
Pin Spacings
description
The ’ACT16646 are 16-bit bus transceivers
consisting of D-type flip-flops and control circuitry
with 3-state outputs arranged for multiplexed
transmission of data directly from the data bus or
from the internal storage registers. The devices
can be used as two 8-bit transceivers or one 16-bit
transceiver. Data on the A or B bus is clocked into
the registers on the low-to-high transition of the
appropriate clock (CLKAB or CLKBA) input.
Figure 1 illustrates the four fundamental busmanagement functions that can be performed
with the bus transceivers and registers.
54ACT16646 . . . WD PACKAGE
74ACT16646 . . . DL PACKAGE
1CLKAB
1SAB
2SAB
2CLKAB
1DIR
GND
1A1
1A2
V
CC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
V
CC
2A7
2A8
GND
2DIR
(TOP VIEW)
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
1OE
1CLKBA
1SBA
GND
1B1
1B2
V
CC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
V
CC
2B7
2B8
GND
2SBA
2CLKBA
2OE
Output-enable (OE
) and direction-control (DIR) inputs are provided to control the transceiver functions. In the
transceiver mode, data present at the high-impedance port may be stored in either register or in both. The select
controls (SAB and SBA) can multiplex stored and real-time (transparent mode) data. The circuitry used for
select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between
stored and real-time data. DIR determines which bus receives data when OE is low. In the isolation mode (OE
high), A data may be stored in one register and/or B data may be stored in the other register.
When an output function is disabled, the input function is still enabled and may be used to store and transmit
data. Only one of the two buses, A or B, may be driven at a time.
The 74ACT16646 is packaged in TI’s shrink small-outline package, which provides twice the functionality of
standard small-outline packages in the same printed-circuit-board area.
The 54ACT16646 is characterized for operation over the full military temperature range of –55°C to 125°C. The
74ACT16646 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1996, Texas Instruments Incorporated
1
Page 2
54ACT16646, 74ACT16646
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS127B – MARCH 1990 – REVISED APRIL 1996
BUS A
DIRLCLKABXCLKBAXSABXSBA
OE
L
REAL-TIME TRANSFER
BUS B TO BUS A
BUS B
L
OE
L
BUS A
DIRHCLKABXCLKBAXSABLSBA
REAL-TIME TRANSFER
BUS A TO BUS B
BUS B
X
BUS A
DIRXCLKAB CLKBAXSABXSBA
X
X
H
X
X
↑
XX
STORAGE FROM
A, B, OR A AND B
↑
↑↑
BUS B
OEOE
X
X
X
X
BUS A
DIRLCLKABXCLKBA
L
L H H or L X H X
TRANSFER STORED DA TA
Figure 1. Bus-Management Functions
H or L
TO A AND/OR B
BUS B
SABXSBA
H
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 3
OPERATION OR FUNCTION
54ACT16646, 74ACT16646
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS127B – MARCH 1990 – REVISED APRIL 1996
FUNCTION TABLE
INPUTS
OE DIR CLKAB CLKBA SAB SBA A1–A8 B1–B8
X X ↑ X X X Input Unspecified Store A, B unspecified
X XX ↑ X X Unspecified Input Store B, A unspecified
H X ↑ ↑ X X Input Input Store A and B data
H X H or L H or L X X Input Input Isolation, hold storage
L L X X X L Output Input Real-time B data to A bus
L L X H or L X H Output Input Stored B data to A bus
L H X X L X Input Output Real-time A data to B Bus
L H H or L X H X Input Output Stored A data to bus
†
The data-output functions may be enabled or disabled by various signals at OE or DIR. Data-input functions are always enabled, i.e., data at
the bus terminals is stored on every low-to-high transition of the clock inputs.
DATA I/O
†
{
{
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
Page 4
54ACT16646, 74ACT16646
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS127B – MARCH 1990 – REVISED APRIL 1996
logic symbol
†
56
1OE
2OE
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
1
55
54
2
3
29
28
30
31
27
26
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
1DIR
1CLKBA
1SBA
1CLKAB C6
1SAB
2DIR
2CLKBA
2SBA
2CLKAB C13
2SAB
G3
3 EN1 [BA]
3 EN2 [AB]
C4
G5
G7
G10
10 EN8 [BA]
10 EN9 [AB]
C11
G12
G14
≥1
1
6D
177
≥1
8
13D
11414
≥1
≥1
155
11D
11212
4D
2
9
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 5
logic diagram (positive logic)
56
1OE
1
1DIR
1SBA
1SAB
55
54
2
3
1CLKBA
1CLKAB
54ACT16646, 74ACT16646
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS127B – MARCH 1990 – REVISED APRIL 1996
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2OE
2DIR
2CLKBA
2SBA
2CLKAB
2SAB
5
6
8
9
10
12
13
14
29
28
30
31
27
26
C1
1D
TG
TG
Seven Channels Identical
to Channel One Above
TG
TG
C1
1D
52
51
49
48
47
45
44
43
B1
B2
B3
B4
B5
B6
B7
B8
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
15
16
17
19
20
21
23
24
TG
TG
C1
1D
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TG
TG
Seven Channels Identical
to Channel One Above
C1
1D
42
41
40
38
37
36
34
33
B1
B2
B3
B4
B5
B6
B7
B8
5
Page 6
54ACT16646, 74ACT16646
UNIT
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS127B – MARCH 1990 – REVISED APRIL 1996
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
Input voltage range, VI (see Note 1) –0.5 V to VCC+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Note 1) –0.5 V to VCC+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
Output clamp current, I
Continuous output current, I
(V
< 0 or VI > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
I
(V
< 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
O
(V
= 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
O
Continuous current through VCC or GND ±400 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum package power dissipation at TA = 55°C (in still air) (see Note 2): DL package 1.4 W. . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils.
stg
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
recommended operating conditions (see Note 3)
54ACT16646 74ACT16646
MIN MAX MIN MAX
V
V
V
V
V
I
OH
I
OL
Dt/D
T
NOTES: 3. Unused inputs must be held high or low to prevent them from floating.
Supply voltage (see Note 4) 4.5 5.5 4.5 5.5 V
CC
High-level input voltage 2 2 V
IH
Low-level input voltage 0.8 0.8 V
IL
Input voltage 0 V
I
Output voltage 0 V
O
High-level output current –24 –24 mA
Low-level output current 24 24 mA
v Input transition rise or fall rate 0 10 0 10 ns/V
Operating free-air temperature –55 125 –40 85 °C
A
4. All VCC and GND pins must be connected to the proper voltage power supply.
CC
CC
0 V
0 V
CC
CC
V
V
†
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other specifications
are design goals. Texas Instruments reserves the right to change or
discontinue these products without notice.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 7
PARAMETER
TEST CONDITIONS
V
UNIT
I
A
V
I
mA
V
I
A
V
I
24 mA
V
UNIT
t
S
CLKAB↑
CLKBA↑
ns
54ACT16646, 74ACT16646
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS127B – MARCH 1990 – REVISED APRIL 1996
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
CC
= –50
= –24
= 50
=
m
{
{
m
{
{
CC
OH
OH
OL
I
I
I
OZ
I
CC
D
C
C
†
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
‡
For I/O ports, the parameter IOZ includes the input leakage current.
§
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
Control inputs VI = VCC or GND 5.5 V ±0.1 ±1 ±1
A or B ports}VO = VCC or GND 5.5 V ±0.5 ±10 ±5
w
I
CC
Control inputs VI = VCC or GND 5 V 4 pF
i
A or B ports VO = VCC or GND 5 V 12 pF
io
OH
IOH = –50 mA
IOH = –75 mA
OL
OL
IOL = 50 mA
IOL = 75 mA
VI = VCC or GND, IO = 0 5.5 V 8 160 80
One input at 3.4 V ,
Other inputs at GND or V
4.5 V 4.4 4.4 4.4
5.5 V 5.4 5.4 5.4
4.5 V 3.94 3.7 3.8
5.5 V 4.94 4.7 4.8
5.5 V 3.85
5.5 V 3.85
4.5 V 0.1 0.1 0.1
5.5 V 0.1 0.1 0.1
4.5 V 0.36 0.5 0.44
5.5 V 0.36 0.5 0.44
5.5 V 1.65
5.5 V 1.65
5.5 V 0.9 1 1 mA
TA = 25°C 54ACT16646 74ACT16646
MIN TYP MAX MIN MAX MIN MAX
m
A
m
A
m
A
timing requirements over recommended ranges of supply voltage and operating free-air
temperature, (unless otherwise noted) (see Figure 2)
TA = 25°C 54ACT16646 74ACT16646
MIN MAX MIN MAX MIN MAX
f
clock
t
w
su
t
h
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other specifications
are design goals. Texas Instruments reserves the right to change or
discontinue these products without notice.
Clock frequency 0 90 0 90 0 90 MHz
Pulse duration, CLKAB or CLKBA high or low 5.5 5.5 5.5 ns
etup time, A before
Hold time, A before CLKAB↑ or B before CLKBA↑ 1.5 1.5 1.5 ns
or B before
Data high 4 4 4
Data low 6 6 6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
Page 8
54ACT16646, 74ACT16646
PARAMETER
UNIT
A or B
B or A
ns
OE
A or B
ns
OE
A or B
ns
CLKBA or CLKAB
A or B
ns
SAB or SBA
A or B
ns
SBA or SAB
A or B
ns
DIR
A or B
ns
DIR
A or B
ns
CpdPower dissipation capacitance per transceiver
C
f
pF
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS127B – MARCH 1990 – REVISED APRIL 1996
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, (unless otherwise noted) (see Figure 2)
FROM TO
(INPUT) (OUTPUT)
f
max
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
†
These parameters are measured with the internal output state of the storage register opposite to that of the bus input.
SAB or SBA
(with A or B high)
SBA or SAB
(with A or B high)
{
{
TA = 25°C 54ACT16646 74ACT16646
MIN TYP MAX MIN MAX MIN MAX
90 90 90 MHz
3.9 7.5 9.4 3.9 11.5 3.9 10.6
3.4 7.6 10.6 3.4 12.2 3.4 11.4
3.2 7.7 10.8 3.2 12.9 3.2 11.9
4.2 9 12.2 4.2 14.6 4.2 13.5
5.3 7.7 9.6 5.3 10.4 5.3 10.2
4.9 7.3 9.2 4.9 10.3 4.9 9.9
4.9 8.9 11.1 4.9 13.1 4.9 12.2
5.1 9 11 5.1 13.1 5.1 12.3
5.2 10.3 13.8 5.2 17.2 5.2 15.6
4.9 8.2 10.6 4.9 12.5 4.9 11.7
4.3 7.8 9.9 4.3 12.1 4.3 11.1
5.9 11.2 14.9 5.9 18.2 5.9 16.7
4.5 9.5 13.6 4.5 16.2 4.5 15.2
4.3 9.2 11.8 4.3 14.2 4.3 13.1
4.5 7.9 10.2 4.5 11.2 4.5 10.8
4.4 7.5 9.8 4.4 10.8 4.4 10.4
operating characteristics, V
p
p
= 5 V, TA = 25°C
CC
PARAMETER TEST CONDITIONS TYP UNIT
p
Outputs enabled
Outputs disabled
= 50 pF,
L
p
= 1 MHz
58
13
p
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other specifications
are design goals. Texas Instruments reserves the right to change or
discontinue these products without notice.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 9
From Output
Under Test
CL = 50 pF
(see Note A)
16-BIT BUS TRANSCEIVERS AND REGISTERS
SCAS127B – MARCH 1990 – REVISED APRIL 1996
PARAMETER MEASUREMENT INFORMATION
2 × V
500 Ω
500 Ω
S1
CC
Open
GND
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
54ACT16646, 74ACT16646
WITH 3-STATE OUTPUTS
Open
2 × V
CC
GND
Input
Input
In-Phase
Output
Out-of-Phase
Output
LOAD CIRCUIT
t
w
1.5 V 1.5 V
VOLTAGE WAVEFORMS
1.5 V 1.5 V
t
PLH
50% V
CC
t
PHL
50% V
CC
VOLTAGE WAVEFORMS
t
PHL
50% V
t
PLH
50% V
3 V
0 V
CC
CC
3 V
0 V
V
V
V
V
OH
OL
OH
OL
Timing Input
Data Input
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
CC
t
PZL
t
PZH
t
su
1.5 V
VOLTAGE WAVEFORMS
1.5 V
t
PLZ
50% V
t
PHZ
50% V
VOLTAGE WAVEFORMS
1.5 V
CC
CC
t
h
1.5 V
1.5 V
20% V
80% V
CC
CC
3 V
0 V
3 V
0 V
3 V
0 V
[
V
V
[
V
OL
OH
0 V
CC
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 2. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
Page 10
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
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pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICA TIONS USING SEMICONDUCT OR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
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intellectual property right of TI covering or relating to any combination, machine, or process in which such
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party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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