The 74ACT04 is an advanced high-speed CMOS
HEX INVERTER fabricated with sub-micron
silicon gate and double-layer metal wiring C
2
MOS
technology.
The internal circuit is composed of 3 stages
including buffer output , which enables high noise
immunity and stable output.
TSSOPDIPSOP
ORDER CODES
PACKAGETUBET & R
DIP74ACT04B
SOP74ACT04M74ACT04MTR
TSSOP74ACT04TTR
The device is designed to interface directly High
Speed CMOS systems with TTL, NMOS and
CMOS output voltage levels.
All inputs and outputs are equipped with
protection circuits against stat ic discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
1/8July 2001
Page 2
74ACT04
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN NoSYMBOLNAME AND FUNCTION
1, 3, 5, 9, 1 1,
13
2, 4, 6, 8, 10,
12
7GNDGround (0V)
14
TRUTH TABLE
ABSOLUTE MAXIMUM RATINGS
SymbolParameterValueUnit
V
V
V
I
I
OK
I
I
or I
CC
T
T
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
Supply Voltage
CC
DC Input Voltage-0.5 to VCC + 0.5
I
DC Output Voltage-0.5 to VCC + 0.5
O
DC Input Diode Current
IK
DC Output Diode Current
DC Output Current
O
DC VCC or Ground Current
GND
Storage Temperature
stg
Lead Temperature (10 sec)
L
1A to 6AData Inputs
1Y to 6YData Outputs
V
CC
Positive Supply Voltage
AY
LH
HL
-0.5 to +7V
V
V
± 20mA
± 20mA
± 50mA
± 200mA
-65 to +150°C
300°C
RECOMMENDED OPERATING CONDITIONS
SymbolParameterValueUnit
V
V
V
T
dt/dv
1) VIN from 0.8V to 2.0V
2/8
Supply Voltage
CC
Input Voltage0 to V
I
Output Voltage0 to V
O
Operating Temperature
op
Input Rise and Fall Time V
= 4.5 to 5.5V (note 1)
CC
4.5 to 5.5V
CC
CC
-55 to 125°C
8ns/V
V
V
Page 3
DC SPECIFICATIONS
Test ConditionValue
T
SymbolParameter
V
CC
(V)
V
V
V
V
I
CCT
I
I
OLD
I
OHD
1) Maxim um test duration 2ms, one output loaded at tim e
2) Incid ent wave switching is guaranteed on transmission l i nes with impe dances as low as 50Ω
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
Input Capacitance
IN
Power Dissipation
PD
Capacitance (note 1)5.0
5.04pF
= 10MHz
f
IN
T
A
-40 to 85°C -55 to 125°C
Min.Typ. Max.Min.Max. Min. Max.
37pF
= CPD x VCC x fIN + ICC/6 (per gate)
CC(opr)
Unit
3/8
Page 4
74ACT04
TEST CIRCUIT
CL = 50pF or equivalent (includes jig and probe capacitance)
R
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