Datasheet 74AC74 Datasheet (Fairchild)

November 1988 Revised February 2005

74AC74 • 74ACT74 Dual D-Type Positive Edge-Triggered Flip-Flop

General Description

The AC/ACT74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and co mplementary (Q, Q Information at the inpu t is tr ansferr ed to th e outp uts on t he positive edge of the clock pul se. Cl ock tr iggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive- going pulse. After the Clock Pulse input threshold voltage has been passed, the Data input is locked out an d i nf orm atio n p resent will not be transferred to the outp uts until the next rising edge of t he Clock Pulse input.

Asynchronous Inputs:

LOW input to S LOW input to C Clear and Set are independent of clock

Simultaneous LOW on C HIGH

(Set) sets Q to HIGH level

D

(Clear) sets Q to LOW level

D

and SD makes both Q and Q

D

) outputs.

Features

■ I

reduced by 50%

CC

■ Output source/sink 24 mA

■ ACT74 has TTL-compatible inputs

Ordering Code:

Order Number

74AC74SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74AC74SC_NL

(Note 1) 74AC74SJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74AC74MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74AC74MTCX_NL

(Note 2) 74AC74PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

74ACT74SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74ACT74SC_NL

(Note 1) 74ACT74SJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ACT74SJX_NL

(Note 2) 74ACT74MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74ACT74PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Device also availab le in Tape and Reel. Specify by appending suffix let te r “X” to the ordering code . Pb-Free package per JECED J-STD-020B.

Note 1: “_NL” indicates lead-free product (per JEDEC J-STD-020B). Note 2: “_NL” indicates lead-free product (per JEDE C J -ST D -020B). Device is av ailable in Tape and Reel only.

Package

Number

M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Descript ion

¥

is a trademark of Fairchild Semiconductor Corporation.

FACT

Connection Diagram Pin Descriptions

Pin Names Description

, D

D

1

2

CP

, CP

1

2

, C

C

D1

D2

, S

S

D1

D2

74AC74 • 74ACT74

Q

, Q1, Q2, Q

1

2

Data In puts Clock Pulse Inputs Direct Clear Inputs Direct Set Inputs Outputs

Logic Symbols

Truth Table

(Each Half)

S

D

LHXXHL HLXXLH LLXXHH HH HH

H HIGH Voltage Level

LOW Voltage Level

L

X

Immaterial



LOW-to-HIGH Clock Transition

(Q0) Previous Q (Q) before LOW-to-HIGH Transition of Clock

Q

0

HHLXQ

Inputs Outputs

CDCP D Q Q



HH L



LLH

0

IEEE/IEC

Q

0

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Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

74AC74 • 74ACT74

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Absolute Maximum Ratings(Note 3) Recommended Operating

Supply Voltage (VCC) DC Input Diode Current (I

V

0.5V

I

VCC  0.5V

V

I

DC Input Voltage (V

)

I

DC Output Diode Current (I

0.5V

V

74AC74 • 74ACT74

O

VCC  0.5V

V

O

DC Output Voltage (V DC Output Source

CC

)

O

or I

or Sink Current (I

DC V

or Ground Current

CC

per Output Pin (I Storage Temperature (T Junction Temperature (T

PDIP 140



0.5V to 7.0V

)

IK



0.5V to VCC  0.5V

)

OK

)

O

GND

)

STG

)

J



0.5V to VCC  0.5V

)

q

C

65q

C to 150qC



20 mA



20 mA



20 mA



20 mA

r

50 mA

r

50 mA

Conditions

Supply Voltage (V

AC 2.0V to 6.0V

ACT 4.5V to 5.5V Input Voltage (V Output Voltage (VO) 0V to V Operating Temperature (TA) Minimum Input Edge Rate (

AC Devices

V

from 30% to 70% of V

IN

VCC @ 3.3V, 4.5V, 5.5V 125 mV/ns Minimum Input Edge Rate (

ACT Devices

V

from 0.8V to 2.0V

IN

@ 4.5V, 5.5V 125 mV/ns

V

CC

Note 3: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system de sign is relia ble over its po wer supply, temperature, and ou tput/inp ut loadi ng varia bles. Fairchild does no t recommend operat ion of FACT

)

CC

) 0V to V

I

'V/'

t)

CC

'V/'

t)

¥

circuits outside databook specifications.

DC Electrical Characteristics for AC

V

Symbol Parameter

V

IH

V

IL

V

OH

V

OL

I

IN

I

OLD

I

OHD

I

CC

(Note 6) Supply Current or GND

Note 4: All outputs loaded; thresholds on input associated with output under test. Note 5: Maximum test dura tio n 2. 0 ms, one output loade d at a time. Note 6: I

Minimum HIGH 3.0 1.5 2.1 2.1 V Level Input 4.5 2.25 3.15 3.15 V or VCC  0.1V Voltage 5.5 2.75 3.85 3.85 Maximum LOW 3.0 1.5 0.9 0.9 V Level Input 4.5 2.25 1.35 1.35 V or VCC  0.1V Voltage 5.5 2.75 1.65 1.65 Minimum HIGH 3.0 2.99 2.9 2.9 Level Output 4.5 4.49 4.4 4.4 V I Voltage 5.5 5.49 5.4 5.4

Maximum LOW 3.0 0.002 0.1 0.1 Level Output 4.5 0.001 0.1 0.1 V I Voltage 5.5 0.001 0.1 0.1

(Note 6) Maximum Input Leakage Current 5.5

Minimum Dynamic 5.5 75 mA V Output Current (Note 5) 5.5 Maximum Quiescent

and ICC @ 3.0V are guaranteed to be less than or eq ual to the respective lim it @ 5. 5V VCC.

IN

CC

(V) Typ Guaranteed Limits

3.0 2.56 2.46 IOH 12 mA

4.5 3.86 3.76 V I

5.5 4.86 4.76 I

3.0 0.36 0.44 IOL 12 mA

4.5 0.36 0.44 V IOL 24 mA

5.5 0.36 0.44 IOL 24 mA (Note 4)

5.5 2.0 20.0

TA 25qCTA 40qC to 85qC

r

0.1

r

1.0



75 mA V

Units Conditions

P

AVI VCC, GND

P

A

40q

0.1V

OUT

0.1V

OUT

50 PA

OUT

VIN VIL or V

24 m

OH

24 m (Note 4)

OH

50 PA

OUT

VIN VIL or V

1.65V Maximum

OLD

3.85V Minimum

OHD

VIN VCC

CC CC

C to 85qC

IH

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DC Electrical Characteristics for ACT

Symbol Parameter

V

IH

Minimum HIGH Level 4.5 1.5 2.0 2.0 Input Voltage 5.5 1.5 2.0 2.0 or VCC  0.1V

V

IL

Maximum LOW Level 4.5 1.5 0.8 0.8 Output Voltage 5.5 1.5 0.8 0.8 or V

V

OH

Minimum HIGH Level 4.5 4.49 4.4 4.4 Output Voltage 5.5 5.49 5.4 5.4

V

OL

Maximum LOW Level 4.5 0.001 0.1 0.1 Output Voltage 5.5 0.001 0.1 0.1

I

IN

Maximum Input Leakage Current

I

CCT

Maximum

ICC/Input I I I

OLD OHD CC

Minimum Dynamic 5.5 75 mA V

Output Current (Note 8) 5.5

Maximum Quiescent

Supply Current or GND

Note 7: All outputs loaded; thresholds on input associated with output under test. Note 8: Maximum test duration 2.0 ms, one output loaded at a time.

VCC TA 25qCTA 40qC to 85qC

(V) Typ Guaranteed Limits

4.5 3.86 3.76 V IOH 24 mA

5.5 4.86 4.76 I

4.5 0.36 0.44 V IOL 24 mA

5.5 0.36 0.44 IOL 24 mA (Note 7)

5.5

5.5 0.6 1.5 mA

5.5 2.0 20.0

74AC74 • 74ACT74

Units Conditions

V

0.1V

OUT

V

0.1V

OUT

V

r

0.1

r

1.0



75 mA V

P

A

P

A

 0.1V

CC

I

50 PA

OUT

VIN VIL or V

24 mA (Note 7)

OH

I

50 PA

OUT

V

VIL or V

IN

VI VCC, GND

VI VCC  2.1V

1.65V Maximum

OLD

3.85V Minimum

OHD

VIN V

CC

IH

AC Electrical Characteristics for AC

V

CC

Symbol Parameter (V)

(Note 9) Min Typ Max Min Max

f

MAX

t

PLH

t

PHL

t

PLH

t

PHL

Note 9: Voltage Range 3.3 is 3.3V r 0.3V

Maximum Clock 3.3 100 125 95

Frequency 5.0 140 160 125

Propagation Delay 3.3 3.5 8.0 12.0 2.5 13.0

CDn or SDn to Qn or Q

n

5.0 2.5 6.0 9.0 2.0 10.0 Propagation Delay 3.3 4.0 10.5 12.0 3.5 13.5 CDn or SDn to Qn or Q

n

5.0 3.0 8.0 9.5 2.5 10.5 Propagation Delay 3.3 4.5 8.0 13.5 4.0 16.0 CPn to Qn or Q

n

5.0 3.5 6.0 10.0 3.0 10.5 Propagation Delay 3.3 3.5 8.0 14.0 3.5 14.5 CPn to Qn or Q

Voltage Range 5.0 is 5.0V

n

r

0.5V

5.0 2.5 6.0 10.0 2.5 10.5

TA 25qCT

40qC to 85qC

A

CL 50 pF CL 50 pF

Units

MHz

ns

5 www.fairchildsemi.com

AC Operating Requirements for AC

Symbol Parameter (V)

t

74AC74 • 74ACT74

t

S

H

W

Set-up Time, HIGH or LOW 3.3 1.5 4.0 4.5 D

to CP

n

Hold Time, HIGH or LOW 3.3 Dn to CP

n

CPn or CDn or S

Dn

Pulse Width 5.0 2.5 4.5 5.0

t

rec

Note 10: Voltage Range 3.3 is 3.3V r 0.3V

Recovery Time 3.3

or SDn to CP 5.0

C

Dn

r

Voltage Range 5.0 is 5. 0V

0.5V

AC Electrical Characteristics for ACT

V

CC

Symbol Parameter (V)

(Note 11)Min TypMaxMinMax

f

MAX

t

PLH

t

PHL

t

PLH

t

PHL

Note 11: Voltage Range 5.0 is 5.0V r 0.5V

Maximum Clock Frequency Propagation Delay CDn or SDn to Qn or Q Propagation Delay CDn or SDn to Qn or Q Propagation Delay

to Qn or Q

CP

n

Propagation Delay CP

to Qn or Q

n

5.0 145 210 125 MHz

n

5.0 3.0 5.5 9.5 2.5 10.5 ns

5.0 3.0 6.0 10.0 3.0 11.5 ns

5.0 4.0 7.5 11.0 4.0 13.0. ns

5.0 3.5 6.0 10.0 3.0 11.5 ns

V

CC

TA 25qCT

40qC to 85qC

A

CL 50 pF CL 50 pF

(Note 10) Typ Guaranteed Minimum

5.0 1.0 3.0 3.0



2.0 0.5 0.5

5.0



1.5 0.5 0.5

3.3 3.0 5.5 7.0



2.5 0 0



2.0 0 0

TA 25qCT

40qC to 85qC

A

CL 50 pF CL 50 pF

Units

ns

Units

AC Operating Requirements for ACT

Symbol Parameter (V)

t

S

t

H

t

W

Set-up Time, HIGH or LOW Dn to CP

n

Hold Time, HIGH or LOW Dn to CP

n

CPn or CDn or S

Dn

Pulse Width

t

rec

Recovery Time CDn or SDn to CP

Note 12: Voltage Range 5.0 is 5.0V r 0.5V

V

CC

(Note 12) Typ Guaranteed Minimum

5.0 1.0 3.0 3.5 ns

5.0

5.0 3.0 5.0 6.0 ns

5.0

TA 25qCT

40qC to 85qC

A

CL 50 pF CL 50 pF



0.5 1.0 1.0 ns



2.5 0 0 ns

Capacitance

Symbol Parameter Typ Units Conditions

C

IN

C

PD

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Input Capacitance 4.5 pF VCC OPEN Power Dissipation Capacitance 35.0 pF VCC 5.0V

Units

Physical Dimensions inches (millimeters) unless otherwise noted

74AC74 • 74ACT74

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Package Number M14A

7 www.fairchildsemi.com

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

74AC74 • 74ACT74

Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

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Package Number M14D

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

74AC74 • 74ACT74

14-Lead Thin Shrin k Small Ou tlin e Pack age (TSSOP), JEDEC MO-153, 4.4mm Wide

Package Number MTC14

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Package Number N14A

74AC74 • 74ACT74 Dual D-Type Positive Edge-Triggered Flip-Flop

Fairchild does not assume any responsibility for use of an y circuitry described, no circuit patent licenses are imp lied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or syste ms which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant inju ry to the user.

2. A critical component in any componen t of a life support device or system whose failu re to perform can be reasonably expected to cause the failure of the li fe su pp ort device or system, or to affect its safety or effectiveness.

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