Datasheet 74AC574 Datasheet (Fairchild)

74AC574 • 74ACT574 Octal D-Type Flip-Flop with 3-STATE Outputs

74AC574 • 74ACT574 Octal D-Type Flip-Flop wit h 3-STATE Outputs

September 1988 Revised March 2005

General Description

The AC/ACT574 is a high-speed , low power oc tal flip-flop with a buffered common C lock (CP) and a buffered com mon Output Enable (OE D-type inputs is stored in the flip-flops on the LOW-to-HIGH Clock (CP) transition.

The AC/ACT574 is functionally identical to the AC /ACT3 74 except for the pinouts.

). The information presented to the

Features

■ I

and IOZ reduced by 50%

CC

■ Inputs and outputs on opposite sides of package

allowing easy interface with microprocessors

■ Useful as input or output port for microprocessors

■ Functionally identical to AC/ACT374

■ 3-STATE outputs for bus-oriented applications

■ Outputs source/sink 24 mA

■ ACT574 has TTL-compatible inputs

Ordering Code:

Order Number Package Number Package Description

74AC574SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74AC574SJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74AC574MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74AC574PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 74ACT574SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74ACT574SJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ACT574MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74ACT574PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Device also availab le in Tape and Reel. Specify by appending suffix let te r “X” to the ordering code . Pb-Free package per JEDEC J-STD-020B.

¥

is a trademark of Fairchild Semiconductor Corporation.

FACT

Logic Symbols

74AC574 • 74ACT574

Connection Diagram

IEEE/IEC

Pin Descriptions

Pin Names Description

D

0–D7

Data Inputs CP Clock Pulse Input OE O

0–O7

3-STATE Output Enable Input

3-STATE Outputs

Function Table

Inputs Internal Outputs Function

CP D Q

OE

HHL NC Z Hold H HH NC Z Hold



H H

L L

L L Z Load



H H Z Load



L L L Data Available



H H H Data Available L H L NC NC No Change in Data L H H NC NC No Change in Data

H HIGH Voltage Level L

LOW Voltage Level Immaterial

X Z

High Impedance



LOW-to-HIGH Transition

No Change

NC

O

N

Functional Description

The AC/ACT574 consi sts of eight edge-tri ggered flip-flo ps with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffere d Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individua l D-type inputs that meet the s etup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With the Ou tpu t En able ( OE

) LOW, the contents of the eight flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high impedance state. Operation of the OE

input does not affect the state of the flip-

flops.

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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Absolute Maximum Ratings(Note 1) Recommended Operating

Supply Voltage (VCC) DC Input Diode Current (I

V

0.5V 20 mA

I

VCC 0.5V

V

I

DC Input Voltage (V DC Output Diode Current (I

0.5V 20 mA

V

O

VCC 0.5V

V

O

DC Output Voltage (V

)

IK

)

I

)

OK

)

O



0.5V to 7.0V



0.5V to VCC 0.5V



0.5V to VCC 0.5V

DC Output Source

or Sink Current (I

DC V

or Ground Current

CC

Per Output Pin (I Storage Temperature (T Junction Temperature (T

)

O

or I

CC

)

GND

STG

J

)

65q

C to 150qC

PDIP 140



20 mA



20 mA

r

50 mA

r

50 mA

Conditions

Supply Voltage (V

AC 2.0V to 6.0V

ACT 4.5V to 5.5V Input Voltage (V Output Voltage (VO)0V to V Operating Temperature (TA) Minimum Input Edge Rate (

AC Devices

V

from 30% to 70% of V

IN

VCC @ 3.3V, 4.5V, 5.5V 125 mV/ns Minimum Input Edge Rate (

ACT Devices

V

from 0.8V to 2.0V

IN

@ 4.5V, 5.5V 125 mV/ns

V

q

C

CC

Note 1: Absolute max imum ratings are those values beyond which damage to the device may oc cur. The databook spe cificat ions shou ld be met , without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT

)

CC

)0V to V

I

40q

C to 85qC

'V/'

t)

CC

'V/'

t)

¥

circuits outside databook specifications.

DC Electrical Characteristics for AC

V

Symbol Parameter

V

IH

V

IL

V

OH

V

OL

IIN (Note 4) Maximum Input Leakage Current 5.5 I

OZ

I

OLD

I

OHD

ICC (Note 4) Maximum Quiescent Supply Current 5.5 4.0 40.0 PAVIN VCC or GND

Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: I

Minimum HIGH Level 3.0 1.5 2.1 2.1 V Input Voltage 4.5 2.25 3.15 3.15 V or VCC  0.1V

5.5 2.75 3.85 3.85 Maximum LOW Level 3.0 1.5 0.9 0.9 V Input Voltage 4.5 2.25 1.35 1.35 V or VCC  0.1V

Minimum HIGH Level 3.0 2.99 2.9 2.9 Output Voltage 4.5 4.49 4.4 4.4 V I

Maximum LOW Level 3.0 0.002 0.1 0.1 Output Voltage 4.5 0.001 0.1 0.1 V I

Maximum VI (OE) VIL, V 3-STATE 5.5 Leakage Current VO VCC, GND Minimum Dynamic 5.5 75 mA V Output Current (Note 3) 5.5

and ICC @ 3.0V are guaranteed to be less than or e qual to the respective l im it @ 5. 5V VCC.

IN

CC

(V) Typ Guaranteed Limits

5.5 2.75 1.65 1.65

5.5 5.49 5.4 5.4

3.0 2.56 2.46 VIN VIL or V

4.5 3.86 3.76 V IOH 12 mA

5.5 4.86 4.76 I

5.5 0.001 0.1 0.1

3.0 0.36 0.44 IOL 12 mA

4.5 0.36 0.44 V IOL 24 mA

5.5 0.36 0.44 IOL 24 mA (Note 2)

TA 25qCTA 40qC to 85qC

r

0.1 r1.0

r

0.25

r

2.5



75 mA V

Units Conditions

0.1V

OUT

0.1V

OUT

50 PA

OUT

IH

24 mA I

OH

IOH 24 mA (Note 2)

OUT

VIN VILor V

P

AVI VCC, GND

P

AVI VCC, V

OLD OHD

OH

50 PA

IH

GND

1.65V

3.85V

74AC574 • 74ACT574

CC CC

IH

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DC Electrical Characteristics for ACT

V

Symbol Parameter

V

IH

Minimum HIGH Level 4.5 1.5 2.0 2.0 Input Voltage 5.5 1.5 2.0 2.0 or VCC  0.1V

V

IL

Maximum LOW Level 4.5 1.5 0.8 0.8 Input Voltage 5.5 1.5 0.8 0.8 or V

V

OH

Minimum HIGH Level 4.5 4.49 4.4 4.4

74AC574 • 74ACT574

V

OL

I

IN

I

OZ

I

CCT

I

]OLD

I

OHD

I

CC

Note 5: All outputs loaded; thresholds on input associated with output under test. Note 6: Maximum test dura tio n 2. 0 ms, one output loade d at a time.

Maximum LOW Level 4.5 0.001 0.1 0.1 Output Voltage 5.5 0.001 0.1 0.1

Maximum Input Leakage Current Maximum 3-STATE Leakage Current VO VCC, GND Maximum ICC/Input 5.5 0.6 1.5 mA VI VCC  2.1V Minimum Dynamic 5.5 75 mA V Output Current (Note 6) 5.5 Maximum Quiescent Supply Current or GND

CC

(V) Typ Guaranteed Limits

5.5 5.49 5.4 5.4

4.5 3.86 3.76 V IOH 24 mA

5.5 4.86 4.76 I

4.5 0.36 0.44 V IOL 24 mA

5.5 0.36 0.44 IOL 24 mA (Note 5)

5.5

5.5 4.0 40.0

TA 25qCT

r

0.1

r

0.25 r2.5

40qC to 85qC

A

Units Conditions

V

VI

r

1.0



75 mA V

P

AVI VCC, GND

P

A

P

A

V

0.1V

OUT

V

0.1V

OUT

 0.1V

CC

50 PA

OUT

VIN VILor V

24 mA (Note 5)

OH

50 PA

OUT

VIN VILor V

VI VIL, V

IH

1.65V

OLD

3.85V

OHD

VIN V

CC

IH

AC Electrical Characteristics for AC

V

CC

Symbol Parameter (V)

f

MAX

Maximum Clock 3.3 75 112 60 Frequency 5.0 95 153 85

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

Note 7: Voltage Range 3.3 is 3.3V r 0.3V

Propagation Delay 3.3 3.5 8.5 13.5 3.5 15.0 CP to O

n

Propagation Delay 3.3 3.5 7.5 12.0 3.5 13.5 CP to O

n

Output Enable Time 3.3 2.5 7.0 11.0 2.5 12.0

Output Enable Time 3.3 3.0 6.5 10.5 3.0 11.5

Output Disable Time 3.3 3.5 7.5 12.0 2.5 13.0

Output Disable Time 3.3 2.0 5.5 9.0 1.5 10.0

r

Voltage Range 5.0 is 5. 0V

0.5V

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(Note 7) Min Typ Max Min Max

5.0 2.0 6.0 9.5 2.0 11.0

5.0 2.0 5.5 8.5 2.0 9.5

5.0 2.0 5.0 8.5 2.0 9.0

5.0 2.0 5.0 8.0 1.5 9.0

5.0 2.0 6.0 9.5 1.5 10.5

5.0 1.0 4.5 7.5 1.0 8.5

TA 25qCT

40qC to 85qC

A

CL 50 pF CL 50 pF

Units

MHz

ns

AC Operating Requirements for AC

V

CC

Symbol Parameter (V)

(Note 8) Typ Guaran teed Minimum

t

S

t

H

t

W

Set-Up Time, HIGH or LOW 3.3 0.5 2.5 3.0

to CP 5.0 0 1.5 2.0

D

n

Hold Time, HIGH or LOW 3.3 D

to CP 5.0 0 1.5 1.5

n

CP Pulse Width 3.3 3.5 6.0 7.0 HIGH or LOW 5.0 2.0 4.0 5.0

Note 8: Voltage Range 3.3 is 3.3V r 0.3V

Voltage Range 5.0 is 5.0V

r

0.5V

AC Electrical Characteristics for ACT

V

CC

Symbol Parameter (V)

(Note 9) Min Typ Max Min Max

f

MAX

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

Note 9: Voltage Range 5.0 is 5.0V r0.5V

Maximum Clock Frequency 5.0 100 110 85 ns Propagation Delay 5.0 2.5 7.0 11.0 2.0 12.0 ns CP to O

n

Propagation Delay 5.0 2.0 6.5 10.0 1.5 11.0 ns CP to O

n

Output Enable Time 5.0 2.0 6.4 9.5 1.5 10.0 ns Output Enable Time 5.0 2.0 6.0 9.0 1.5 10.0 ns Output Disable Time 5.0 2.0 7.0 10.5 1.5 11.5 ns Output Disable Time 5.0 2.0 5.5 8.5 1.5 9.0 ns

TA 25qCT C

50 pF CL 50 pF

L



0.5 1.5 1.5

TA 25qCT

40qC to 85qC

A

40qC to 85qC

A

CL 50 pF CL 50 pF

74AC574 • 74ACT574

Units

ns

Units

AC Operating Requirements for ACT

Symbol Parameter (V)

t

S

Set-Up Time, HIGH or LOW Dn to CP

t

H

t

W

Hold Time, HIGH or LOW

to CP

D

n

CP Pulse Width HIGH or LOW

Note 10: Voltage Range 5.0 is 5.0V r 0.5V

V

(Note 10) Typ Guaranteed Minimum

5.0

5.0 2.5 4.0 ns

TA 25qCTA 40qC to 85qC

CC

C

50 pF CL 50 pF

L

5.0 1.5 2.5 ns



0.5 1.0 ns

Capacitance

Symbol Parameter Typ Units Conditions

C

IN

C

PD

Input Capacitance 4.5 pF VCC OPEN Power Dissipation Capacitance 40.0 pF VCC 5.0V

Units

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Physical Dimensions inches (millimeters) unless otherwise noted

74AC574 • 74ACT574

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

Package Number M20B

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

74AC574 • 74ACT574

Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M20D

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

74AC574 • 74ACT574

20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

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Package Number MTC20

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

74AC574 • 74ACT574 Octal D-Type Flip-Flop with 3-STATE Outputs

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Fairchild does not assume any responsibility for use of any circ uitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

1. Life support de vices o r syst ems are dev ic es or syste ms which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provide d in the l abe ling, can be reasonably expected to result in a significant injury to the user.

Package Number N20A

2. A critica l compo nen t in any compo nent o f a l ife supp ort device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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