Datasheet 74AC541SJX, 74AC541SJ, 74AC541SCX, 74AC541SC, 74AC541PC Datasheet (Fairchild Semiconductor)

© 1999 Fairchild Semiconductor Corporation DS009967 www.fairchildsemi.com

November 1988
Revised October 1999

74AC541 • 74ACT541 Octal Buffer/Line Driver with 3-STATE Outputs

74AC541 • 74ACT541
Octal Buffer/Line Driver with 3-STATE Outputs

General Description

The 74AC541 and 74 ACT541 are octal buffer/li ne drivers
designed to be em ployed as mem ory a nd ad dress d rivers,
clock drivers and bus oriented transmitter/receivers.

These devices are similar in fu nction to the 74AC244 a nd
74ACTC244 while providing flow-through architecture
(inputs on opposite side from outputs). This pinout arrange­ment makes these devices esp ecially useful as an outp ut
port for microprocessors, allowing ease of layout and
greater PC board density.

Features

■ ICC and IOZ reduced by 50%

■ 3-STATE outputs

■ Inputs and outputs opposite side of package, allowing

easier interface to microprocessors

■ Output source/sink 24 mA

■ 74AC541 is a non-inverting option of the 74AC540

■ 74ACT541 has TTL-compatible inputs

Ordering Code:

Device also available in Tape and Reel. Specify by appending s uffix let te r “X” to the ordering code.

Logic Symbol

IEEE/IEC

Connection Diagram

Truth Table

H = HIGH Voltage Level X = Immaterial L = LOW Voltage Level Z = High Impedance

FACT is a trade m ark of F airchild Semicondu ctor Corporation.

Order Number Package Number Package Description

74AC541SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74AC541SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC541MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC541PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
74ACT541SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ACT541MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT541PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Inputs

Outputs

OE

1

OE

2

I

L L HH
H X XZ
X H XZ
L L LL

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74AC541 • 74ACT541

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: Absolute maximum ratings are those values beyond which dam-

age to the device may occu r. The databook specificati ons should be met,
without exception, t o ensure that the system design is reliab le over its
power supply, temperature, an d output/input loading variables. Fairc hild
does not recommend operation of FACT circuits outside databook specifi­cations.

DC Electrical Characteristics for AC

Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum te st duration 2.0 ms, one ou t put loaded at a time.
Note 4: I

IN

and ICC @ 3.0V are guaranteed to be less than or equa l to th e respective limit @ 5.5V VCC.

Supply Voltage (VCC) −0.5V to +7.0V
DC Input Diode Current (I

IK

)

V

I

= −0.5V −20 mA

V

I

= VCC + 0.5V +20 mA

DC Input Voltage (V

I

) −0.5V to VCC + 0.5V

DC Output Diode Current (I

OK

)

V

O

= −0.5V −20 mA

V

O

= VCC + 0.5V +20 mA

DC Output Voltage (V

O

) −0.5V to VCC + 0.5V
DC Output Source
or Sink Current (I

O

) ± 50 mA

DC V

CC

or Ground Current

per Output Pin (I

CC

or I

GND

) ± 50 mA

Storage Temperature (T

STG

) −65°C to +150°C

Junction Temperature (T

J

)

PDIP 140°C

Supply Voltage (V

CC

)
AC 2.0V to 6.0V
ACT 4.5V to 5.5V

Input Voltage (V

I

) 0V to V

CC

Output Voltage (VO) 0V to V

CC

Operating Temperature (TA) −40°C to +85°C
Minimum Input Edge Rate (∆V/∆t) 125 mV/ns

AC: V

IN

from 30% to 70% of V

CC

VCC @ 3.3V, 4.5V, 5.5V

ACT:V

IN

from 0.8V to 2.0V

V

CC

@ 4.5V, 5.5V

Symbol Parameter

V

CC

TA = +25°CTA = −40°C to +85°C

Units Conditions

(V) Typ Guaranteed Limits

V

IH

Minimum HIGH Level 3.0 1.5 2.1 2.1

V

V

OUT

= 0.1V

Input Voltage 4.5 2.25 3.15 3.15 or VCC − 0.1V

5.5 2.75 3.85 3.85

V

IL

Maximum LOW Level 3.0 1.5 0.9 0.9

V

V

OUT

= 0.1V

Input Voltage 4.5 2.25 1.35 1.35 or VCC − 0.1V

5.5 2.75 1.65 1.65

V

OH

Minimum HIGH Level 3.0 2.99 2.9 2.9

VOutput Voltage 4.5 4.49 4.4 4.4 I

OUT

= −50 µA

5.5 5.49 5.4 5.4

V

VIN = VIL or V

IH

3.0 2.56 2.46 IOH = −12 mA

4.5 3.86 3.76 IOH = −24 mA

5.5 4.86 4.76 IOH = −24 mA (Note 2)

V

OL

Maximum LOW Level 3.0 0.002 0.1 0.1

V

Output Voltage 4.5 0.001 0.1 0.1 I

OUT

= 50 µA

5.5 0.001 0.1 0.1

V

VIN = VIL or V

IH

3.0 0.36 0.44 IOL = 12 mA

4.5 0.36 0.44 IOL = 24 mA

5.5 0.36 0.44 IOL = 24 mA (Note 2)

IIN (Note 4) Maximum Input Leakage Current 5.5 ± 0.1 ± 1.0 µA VI = V

CC

, GND

I

OZ

Maximum 3- STATE

µA

VI (OE) = V

IL

, V

IH

Leakage Current 5.5 ±0.25 ±2.5 VI = VCC, GND

VO = VCC, GND

I

OLD

Minimum Dynamic 5.5 75 mA V

OLD

= 1.65V Max

I

OHD

Output Current (Note 3) 5.5 −75 mA V

OHD

= 3.85V Min

ICC (Note 4) Maximum Quiescent Supply Current 5.5 4.0 40.0 µAVIN = VCC or GND

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74AC541 • 74ACT541

AC Electrical Characteristics for AC

Note 5: Voltage Range 3.3 is 3.3V ± 0.3V

Voltage Range 5.0 is 5.0V ± 0.5V

DC Electrical Characteristics for ACT

Note 6: All outputs loaded; thresholds on input associated with out put under test.
Note 7: Maximum test duration 2.0 ms, one output loaded at a time.

V

CC

TA = +25°CT

A

= −40°C to +85°C

Symbol Parameter (V)

C

L

= 50 pF CL = 50 pF

Units

(Note 5) Min Typ Max Min Max

t

PLH

Propagation Delay 3.3 2.0 5.5 8.0 1.5 9.0

ns

Data to Output 5.0 1.5 4.0 6.0 1.0 6.5

t

PHL

Propagation Delay 3.3 2.0 5.5 8.0 1.5 8.5

ns

Data to Output 5.0 1.5 4.0 6.0 1.0 6.5

t

PZH

Output Enable Time 3.3 3.0 8.0 11.5 3.0 12.5

ns

5.0 2.0 6.0 8.5 1.5 9.5

t

PZL

Output Enable Time 3.3 2.5 7.0 10.0 2.5 11.5

ns

5.0 1.5 5.5 7.5 1.0 8.5

t

PHZ

Output Disable Time 3.3 3.5 9.0 12.5 2.5 14.0

ns

5.0 2.0 7.0 9.5 1.0 10.5

t

PLZ

Output Disable Time 3.3 2.5 6.5 9.5 2.0 10.5

ns

5.0 2.0 5.5 7.5 1.0 8.5

Symbol Parameter

V

CC

TA = +25°CT

A

= −40°C to +85°C

Units Conditions

(V) Typ Guaranteed Limits

V

IH

Minimum HIGH Level 4.5 1.5 2.0 2.0

V

V

OUT

= 0.1V

Input Voltage 5.5 1.5 2.0 2.0 or V

CC

− 0.1V

V

IL

Maximum LOW Level 4.5 1.5 0.8 0.8

V

V

OUT

= 0.1V

Input Voltage 5.5 1.5 0.8 0.8 or VCC − 0.1V

V

OH

Minimum HIGH Level 3.0 2.99 2.9 2.9

VI

OUT

= −50 µA

Output Voltage 4.5 4.49 4.4 4.4

4.5 3.86 3.76
V

VIN = VIL or V

IH

5.5 4.86 4.76 IOH = −24 mA

IOH = −24 mA (Note 6)

V

OL

Maximum LOW Level 3.0 0.002 0.1 0.1

VI

OUT

= 50 µA

Output Voltage 4.5 0.001 0.1 0.1

4.5 0.36 0.44
V

VIN = VIL or V

IH

5.5 0.36 0.44 IOH = 24 mA

IOH = 24 mA (Note 6)

I

IN

Maximum Input

5.5 ± 0.1 ± 1.0 µA VI = V

CC

, GND

Leakage Current

I

OZ

Maximum 3- STATE

5.5 ±0.25 ±2.5 µA

VI = V

IL

, V

IH

Leakage Current VO = VCC, GND

I

CCT

Maximum ICC/Input 5.5 0.6 1.5 mA VI = VCC − 2.1V

I

OLD

Minimum Dynamic 5.5 75 mA V

OLD

= 1.65V Max

I

OHD

Output Current (Note 7) 5.5 −75 mA V

OHD

= 3.85V Min

I

CC

Maximum Quiescent

5.5 4.0 40.0 µAVIN = VCC or GND

Supply Current

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74AC541 • 74ACT541

AC Electrical Characteristics for ACT

Note 8: Voltage Range 5.0 is 5. 0V ± 0.5V

Capacitance

V

CC

TA = +25°CT

A

= −40°C to +85°C

Symbol Parameter (V)

C

L

= 50 pF CL = 50 pF

Units

(Note 8) Min Typ Max Min Max

t

PLH

Propagation Delay

5.0

2.04.57.02.07.5
ns

t

PHL

Data to Output 2.0 5.5 7.0 2.0 7.5

t

PZH

Output Enable Time

5.0

2.05.09.02.09.5
ns

t

PZL

2.06.59.02.09.5

t

PHZ

Output Disable Time

5.0

1.55.57.51.58.0
ns

t

PLZ

1.55.57.51.58.0

Symbol Parameter Typ Units Conditions

C

IN

Input Capacitance 4.5 pF VCC = OPEN

C

PD

Power Dissipation Capacitance for AC 30.0

pF VCC = 5.0V

Power Dissipation Capacitance for ACT 70.0

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74AC541 • 74ACT541

Physical Dimensions inches (millimeters) unless otherwise noted

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body

Package Number M20B

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74AC541 • 74ACT541

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M20D

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74AC541 • 74ACT541

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Package Number MTC20

www.fairchildsemi.com 8

74AC541 • 74ACT541 Octal Buffer/Line Driver with 3-STATE Outputs

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Package Number N20A

Fairchild does not assume any responsibility for use of any circuitry described, no circuit pate nt licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:

1. Life support de vices o r systems a re devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea­sonably expected to result in a significant inju ry to the
user.

2. A critical com ponent in any com ponen t of a life supp ort
device or system whose failu re to perform can be rea­sonably expected to ca use the fa i lure of the life su pp ort
device or system, or to affect its safety or effectiveness.

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