Datasheet 74AC373SJX, 74AC373SJ, 74AC373SCX, 74AC373SC, 74AC373PC Datasheet (Fairchild Semiconductor)
...Page 1
© 1999 Fairchild Semiconductor Corporation DS009958 www.fairchildsemi.com
November 1988
Revised November 1999
74AC373 • 74ACT373 Octal Transparent Latch with 3-STATE Outputs
74AC373 • 74ACT373
Octal Transparent Latch with 3-STATE Outputs
General Description
The AC/ACT373 consists of eight latches with 3-STATE
outputs for bus organized system applications. The flipflops appear transp arent to the data when Latch Enable
(LE) is HIGH. When LE is LOW, the data that meet s the
setup time is latched. Data appea rs on the bus when the
Output Enable (OE
) is LOW. When OE is HIGH, the bus
output is in the high impedance state.
Features
■ ICC and IOZ reduced by 5 0%
■ Eight latches in a single package
■ 3-STATE outputs for bus interfacing
■ Outputs source/sink 24 mA
■ ACT373 has TTL-compatible inputs
Ordering Code:
Device also available in Tape and Reel. Specify by appending su ffix le tter “X” to the ordering inform ation
Logic Symbols
IEEE/IEC
Connection Diagram
Pin Descriptions
FACT is a trademark of Fairchild Semiconductor Corporation.
Order Number Package Number Package Description
74AC373SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74AC373SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC373MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC373PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
74ACT373SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ACT373SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT373MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74ACT373MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT373PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Pin Names Description
D
0–D7
Data Inputs
LE Latch Enable Input
OE
Output Enable Input
O
0–O7
3-STATE Latch Outputs
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74AC373 • 74ACT373
Functional Description
The AC/ACT373 contains eight D-type latches with 3STATE standard outputs. When the Latch Enable (LE)
input is HIGH, data on th e D
n
inputs enters the latches. In
this condition the latches ar e transparen t, i.e., a la tch output will change state each time its D-type in put changes.
When LE is LOW, the latches sto re the information that
was present on the D-typ e inputs a setup time preceding
the HIGH-to-LOW tr ansition of LE . The 3-STATE standard
outputs are controlled by the Output Enable (OE
) input.
When OE
is LOW, the standard outputs are in the 2-state
mode. When OE
is HIGH, the standard outputs are in the
high impedance mode but this does not interfere with
entering new data into the latches.
Tr uth Table
H = HIGH Voltage Level
L = LOW Voltage Level
Z = High Impedance
X = Immaterial
O
0
= Previous O0 before HIGH-to-LOW transition of Latch Enable
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Inputs Outputs
LE OE D
n
O
n
XHX Z
HLL L
HLH H
LLX O
0
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74AC373 • 74ACT373
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
Note 1: Absolute max imum ratings are those values beyond w hich damage
to the device may occu r. The databook spe cificatio ns shou ld be met, wit hout exception, to ensure that the system de sign is relia ble over its p ower
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specif ic at ions.
DC Electrical Characteristics for AC
Note 2: All outputs loaded, thres holds on input associate d w it h output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: I
IN
and ICC @ 3.0V are guaranteed to be less than or equa l t o th e respective limit @ 5.5V VCC.
Supply Voltage (VCC) −0.5V to +7.0V
DC Input Diode Current (I
IK
)
V
I
= −0.5V −20 mA
V
I
= VCC + 0.5V +20 mA
DC Input Voltage (V
I
) −0.5V to VCC + 0.5V
DC Output Diode Current (I
OK
)
V
O
= −0.5V −20 mA
V
O
= VCC + 0.5V +20 mA
DC Output Voltage (V
O
) −0.5V to VCC + 0.5V
DC Output Source
or Sink Current (I
O
) ± 50 mA
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
) ± 50 mA
Storage Temperature (T
STG
) −65°C to +150°C
Junction Temperature (T
J
)
PDIP 140°C
Supply Voltage (V
CC
)
AC 2.0V to 6.0V
ACT 4.5V to 5.5V
Input Voltage (V
I
)0V to V
CC
Output Voltage (VO)0V to V
CC
Operating Temperature (TA) −40°C to +85°C
Minimum Input Edge Rate (∆V/∆t)
AC Devices
V
IN
from 30% to 70% of V
CC
VCC @ 3.3V, 4.5V, 5.5V 125 mV/ns
Minimum Input Edge Rate (∆V/∆t)
ACT Devices
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V 125 mV/ns
Symbol Parameter
V
CC
(V)
T
A
= +25°CTA = −40°C to +85°C
Units Conditions
Typ Guaranteed Limits
V
IH
Minimum HIGH Level 3.0 1.5 2.1 2.1 V
OUT
= 0.1V
Input Voltage 4.5 2.25 3.15 3.15 V or VCC − 0.1V
5.5 2.75 3.85 3.85
V
IL
Maximum LOW Level 3.0 1.5 0.9 0.9 V
OUT
= 0.1V
Input Voltage 4.5 2.25 1.35 1.35 V or VCC − 0.1V
5.5 2.75 1.65 1.65
V
OH
Minimum HIGH Level 3.0 2.99 2.9 2.9
Output Voltage 4.5 4.49 4.4 4.4 V I
OUT
= −50 µA
5.5 5.49 5.4 5.4
VIN = VIL or V
IH
3.0 2.56 2.46 IOH = −12 mA
4.5 3.86 3.76 V I
OH
= −24 mA
5.5 4.86 4.76 I
OL
= −24 mA (Note 2)
V
OL
Maximum LOW Level 3.0 0.002 0.1 0.1
Output Voltage 4.5 0.001 0.1 0.1 V I
OUT
= 50 µA
5.5 0.001 0.1 0.1
VIN = VIL or V
IH
3.0 0.36 0.44 IOL = 12 mA
4.5 0.36 0.44 V IOL = 24 mA
5.5 0.36 0.44 IOL = 24 mA (Note 2)
I
IN
(Note 4) Maximum Input Leakage Current 5.5 ± 0.1 ± 1.0 µAVI = VCC, GND
I
OZ
Maximum 3-STATE Current VI (OE) = VIL, V
IH
5.5 ±0.25 ± 2.5 µAVI = VCC, GND
VO = VCC, GND
I
OLD
Minimum Dynamic Output Current
(Note 3)
5.5 75 mA V
OLD
= 1.65V Max
I
OHD
5.5 −75 mA V
OHD
= 3.85V Min
I
CC
(Note 4) Maximum Quiescent Supply Current 5.5 4.0 40.0 µAVIN = VCC or GND
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74AC373 • 74ACT373
DC Electrical Characteristics for ACT
Note 5: All outputs loaded; thresholds on input assoc iat ed with output under tes t.
Note 6: Maximum test duratio n 2. 0 ms, one output loaded at a time.
AC Electrical Characteristics for AC
Note 7: Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
Symbol Parameter
V
CC
TA = +25°CT
A
= −40°C to +85°
Units Conditions
(V) Typ Guaranteed Limits
V
IH
Minimum HIGH Level 4.5 1.5 2.0 2.0
V
V
OUT
= 0.1V
Input Voltage 5.5 1.5 2.0 2.0 or VCC − 0.1V
V
IL
Maximum LOW Level 4.5 1.5 0.8 0.8
V
V
OUT
= 0.1V
Input Voltage 5.5 1.5 0.8 0.8 or V
CC
− 0.1V
V
OH
Minimum HIGH Level 4.5 4.49 4.4 4.4
VI
OUT
= −50 µA
Output Voltage 5.5 5.49 5.4 5.4
VIN = VIL or V
IH
4.5 3.86 3.76 V IOH = −24 mA
5.5 4.86 4.76 I
OH
= −24 mA (Note 5)
V
OL
Maximum LOW Level 4.5 0.001 0.1 0.1
VI
OUT
= 50 µA
Output Voltage 5.5 0.001 0.1 0.1
VIN = VIL or V
IH
4.5 0.36 0.44 V IOL = 24 mA
5.5 0.36 0.44 IOL = 24 mA (Note 5)
I
IN
Maximum Input
5.5 ± 0.1 ± 1.0 µAVI = VCC, GND
Leakage Current
I
OZ
Maximum 3-STATE
5.5 ± 0.25 ± 2.5 µA
VI = VIL, V
IH
Current VO = VCC, GND
I
CCT
Maximum ICC/Input 5.5 0.6 1.5 mA VI = VCC − 2.1V
I
OLD
Minimum Dynamic 5.5 75 mA V
OLD
= 1.65V Max
I
OHD
Output Current (Note 6) 5.5 −75 mA V
OHD
= 3.85V Min
I
CC
Maximum Quiescent
5.5 4.0 40.0 µA
VIN = V
CC
Supply Current or GND
V
CC
TA = +25°CT
A
= −40°C to +85°C
Symbol Parameter (V)
CL = 50 pF CL = 50 pF
Units
(Note 7) Min Typ Max Min Max
t
PLH
Propagation Delay 3.3 1.5 10.0 13.5 1.5 15.0
ns
Dn to O
n
5.0 1.5 7.0 9.5 1.5 10.5
t
PHL
Propagation Delay 3.3 1.5 9.5 13.0 1.5 14.5
ns
Dn to O
n
5.0 1.5 7.0 9.5 1.5 10.5
t
PLH
Propagation Delay 3.3 1.5 10.0 13.5 1.5 15.0
ns
LE to O
n
5.0 1.5 7.5 9.5 1.5 10.5
t
PHL
Propagation Delay 3.3 1.5 9.5 12.5 1.5 14.0
ns
LE to O
n
5.0 1.5 7.0 9.5 1.5 10.5
t
PZH
Output Enable Time 3.3 1.5 9.0 11.5 1.0 13.0
ns
5.0 1.5 7.0 8.5 1.0 9.5
t
PZL
Output Enable Time 3.3 1.5 8.5 11.5 1.0 13.0
ns
5.0 1.5 6.5 8.5 1.0 9.5
t
PHZ
Output Disable Time 3.3 1.5 10.0 12.5 1.0 14.5
ns
5.0 1.5 8.0 11.0 1.0 12.5
t
PLZ
Output Disable Time 3.3 1.5 8.0 11.5 1.0 12.5
ns
5.0 1.5 6.5 8.5 1.0 10.0
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74AC373 • 74ACT373
AC Operating Requirements for AC
Note 8: Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
AC Electrical Characteristics for ACT
Note 9: Voltage Range 5.0 is 5.0V ± 0.5V
AC Operating Requirements for ACT
Note 10: Voltage Ran ge 5.0 is 5.0V ± 0.5V
Capacitance
V
CC
TA = +25°CT
A
= −40°C to +85°C
Symbol Parameter (V)
C
L
= 50 pF CL = 50 pF
Units
(Note 8) Typ Guaranteed Minimum
t
S
Setup Time, HIGH or LOW 3.3 3.5 5.5 6.0
ns
D
n
to LE 5.0 2.0 4.0 4.5
t
H
Hold Time, HIGH or LOW 3.3 −3.0 1.0 1.0
ns
D
n
to LE 5.0 −1.5 1.0 1.0
t
W
LE Pulse Width, 3.3 4.0 5.5 6.0
ns
HIGH 5.0 2.0 4.0 4.5
V
CC
TA = +25°CT
A
= −40°C to +85°C
Symbol Parameter (V)
CL = 50 pF CL = 50 pF
Units
(Note 9) Min Typ Max Min Max
t
PLH
Propagation Delay
5.0 2.5 8.5 10.0 1.5 11.5 ns
Dn to O
n
t
PHL
Propagation Delay
5.0 2.0 8.0 10.0 1.5 11.5 ns
Dn to O
n
t
PLH
Propagation Delay
5.0 2.5 8.5 11.0 2.0 11.5 ns
LE to O
n
t
PHL
Propagation Delay
5.0 2.0 8.0 10.0 1.5 11.5 ns
LE to O
n
t
PZH
Output Enable Time 5.0 2.0 8.0 9.5 1.5 10.5 ns
t
PZL
Output Enable Time 5.0 2.0 7.5 9.0 1.5 10.5 ns
t
PHZ
Output Disable Time 5.0 2.5 9.0 11.0 2.5 12.5 ns
t
PLZ
Output Disable Time 5.0 1.5 7.5 8.5 1.0 10.0 ns
V
CC
TA = +25°CT
A
= −40°C to +85°C
Symbol Parameter (V)
C
L
= 50 pF CL = 50 pF
Units
(Note 10) Typ Guaranteed Minimum
t
S
Setup Time, HIGH or LOW
5.0 0.8 2.5 3.5 ns
Dn to LE
t
H
Hold Time, HIGH or LOW
5.0 0 0 1.0 ns
Dn to LE
t
W
LE Pulse Width, HIGH 5.0 2.0 7.0 8.0 ns
Symbol Parameter Typ Units Conditions
C
IN
Input Capacitance 4.5 pF VCC = OPEN
C
PD
Power Dissipation Capacitance 40.0 pF VCC = 5.0V
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74AC373 • 74ACT373
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
Package Number M20B
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74AC373 • 74ACT373
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
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74AC373 • 74ACT373
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
Package Number MSA20
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74AC373 • 74ACT373
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Sm all Ou tline Pa ck age (TS SO P), JE DE C MO-153, 4.4mm Wide
Package Number MTC20
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74AC373 • 74ACT373 Octal Transparent Latch with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitr y described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant inju ry to the
user.
2. A critical component in any compon ent of a lif e supp ort
device or system whose failure t o perform can be reasonably expected to ca use the failure of the life supp ort
device or system, or to affect its safety or effectiveness.
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