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© 1999 Fairchild Semiconductor Corporation DS009955 www.fairchildsemi.com
November 1988
Revised November 1999
74AC280 9-Bit Parity Generator/Checker
74AC280
9-Bit Parity Generator/Checker
General Description
The AC280 is a high-sp eed parity generator/checker th at
accepts nine bits of input data and detects whether an
even or an odd number of these inputs is HIGH. If a n even
number of inputs is HIGH, the Sum Even output is HIGH. If
an odd number is HIGH, the Sum Even output is LOW. The
Sum Odd output is t he complemen t of the Sum Even output.
Features
■ ICC reduced by 50%
■ 9-bit width for memory applications
■ AC280: 5962-92201
Ordering Code:
Devices also availab le in Tape and Reel. Specify by appending su ffix let te r “X” to the ordering code.
Logic Symbols
IEEE/IEC
Pin Descriptions
Connection Diagram
Truth Table
H = HIGH Voltage Level
L = LOW Voltage Level
FACT is a trademark of Fairchild Semiconductor Corporation.
Order Number Package Number Package Description
74AC280SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body
74AC280SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Pin Names Description
I
0–I8
Data Inputs
∑
Ο
Odd Parity Output
∑
Ε
Even Parity Output
Number of Outputs
HIGH Inputs
∑ Even ∑ Odd
I
0–I8
0, 2, 4, 6, 8 H L
1, 3, 5, 7, 9 L H
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74AC280
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74AC280
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
Note 1: Absolute max imum ratings are those values beyond w hich damage
to the device may occu r. The databook spe cificatio ns shou ld be met, wit hout exception, to ensure that the system de sign is relia ble over its p ower
supply, temperature, output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications.
DC Electrical Characteristics
Note 2: All outputs loaded; thres holds on input associate d w it h output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: I
IN
and ICC @ 3.0V are guaranteed to be less than or equa l t o th e respective limit @ 5.5V VCC.
Supply Voltage (VCC) −0.5V to +7.0V
DC Input Diode Current (I
IK
)
V
I
= −0.5V −20 mA
V
I
= VCC + 0.5V +20 mA
DC Input Voltage (V
I
) −0.5V to VCC + 0.5V
DC Output Diode Current (I
OK
)
V
O
= −0.5V −20 mA
V
O
= VCC + 0.5V +20 mA
DC Output Voltage (V
O
) −0.5V to VCC + 0.5V
DC Output Source
or Sink Current (I
O
) ±50 mA
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
) ±50 mA
Storage Temperature (T
STG
) −65°C to +150°C
Junction Temperature (T
J
)
PDIP 140°C
Supply Voltage (V
CC
) 2.0V to 6.0V
Input Voltage (V
I
)0V to V
CC
Output Voltage (VO)0V to V
CC
Operating Temperature (TA) −40°C to +85°C
Minimum Input Edge Rate (∆V/∆t)
V
IN
from 30% to 70% of V
CC
VCC @ 3.3V, 4.5V, 5.5V 125 mV/ns
Symbol Parameter
V
CC
TA = +25°CTA = −40°C to+85°C
Units Conditions
(V) Typ Guaranteed Limits
V
IH
Minimum HIGH Level 3.0 1.5 2.1 2.1 V
OUT
= 0.1V
Input Voltage 4.5 2.25 3.15 3.15 V or VCC − 0.1V
5.5 2.75 3.85 3.85
V
IL
Maximum LOW Level 3.0 1.5 0.9 0.9 V
OUT
= 0.1V
Input Voltage 4.5 2.25 1.35 1.35 V or VCC − 0.1V
5.5 2.75 1.65 1.65
V
OH
Minimum HIGH Level 3.0 2.99 2.9 2.9
Output Voltage 4.5 4.49 4.4 4.4 V I
OUT
= −50 µA
5.55.495.4 5.4
VIN = VIL or V
IH
3.0 2.56 2.46 IOH = −12 mA
4.5 3.86 3.76 V I
OH
= −24 mA
5.5 4.86 4.76 IOH = −24 mA (Note 2)
V
OL
Maximum LOW Level 3.0 0.002 0.1 0.1
Output Voltage 4.5 0.001 0.1 0.1 V I
OUT
= 50 µA
5.5 0.001 0.1 0.1
VIN = VIL or V
IH
3.0 0.36 0.44 IOL = 12 mA
4.5 0.36 0.44 V IOL = 24 mA
5.5 0.36 0.44 IOL = 24 mA (Note 2)
I
IN
Maximum Input
5.5 ±0.1 ±1.0 µAVI = VCC, GND
Leakage Current
I
OLD
Minimum Dynamic 5.5 75 mA V
OLD
= 1.65V Max
I
OHD
Output Current (Note 3) 5.5 −75 mA V
OHD
= 3.85V Min
I
CC
Maximum Quiescent
5.5 4.0 40.0 µA
VIN = V
CC
(Note 4) Supply Current or GND
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74AC280
AC Electrical Characteristics
Note 5: Voltage range 3.3 is 3.3V ± 0.3V.
Voltage range 5.0 is 5.0V ± 0.5V.
Capacitance
Symbol Parameter
V
CC
T
A
= +25°CT
A
= −40°C to +85°C
Units
(V)
C
L
= 50 pF CL = 50 pF
(Note 5) Min Typ Max Min Max
t
PLH
Propagation Delay 3.3 5.0 10.5 17.0 4.0 18.5
ns
t
PHL
In to ∑
Ε
5.0 3.0 7.5 13.0 2.0 14.5
t
PLH
Propagation Delay 3.3 5.0 12.0 17.0 4.0 18.5
ns
t
PHL
In to ∑
Ο
5.0 3.0 8.5 13.0 2.0 14.5
Symbol Parameter Typ Units Conditions
C
IN
Input Capacitance 4.5 pF VCC = OPEN
C
PD
Power Dissipation Capacitance 75.0 pF VCC = 5.0V
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74AC280
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body
Package Number M14A
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74AC280 9-Bit Parity Generator/Checker
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
Fairchild does not assume any responsibility for use of any circuitr y described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant inju ry to the
user.
2. A critical component in any compon ent of a lif e supp ort
device or system whose failure t o perform can be reasonably expected to ca use the failure of the life supp ort
device or system, or to affect its safety or effectiveness.
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