Datasheet 74AC175 Datasheet (Fairchild)

74AC175 • 74ACT175 Quad D-Type Flip-Flop

November 1988 Revised November 1999

General Description

The AC/ACT175 is a hi g h-s pee d q uad D-type flip-flop . T he device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D-type inputs is stored during the LOW-to-HIGH clock transition. Both true and comple mented outputs of each flipflop are provided. A Master Reset input resets all flip-flops, independent of the Clock or D-type inputs, when LOW.

Features

■ ICC reduced by 50%

■ Edge-triggered D-type inputs

■ Buffered positive edge-triggered cl ock

■ Asynchronous common reset

■ True and complement output

■ Outputs source/sink 24 mA

■ ACT175 has TTL-compatible inputs

Ordering Code:

Order Number Package Number Package Description

74AC175SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body 74AC175SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74AC175MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74AC175PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide 74ACT175SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body 74ACT175SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ACT175MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74ACT175PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the or dering code.

Logic Symbols

Connection Diagram

IEEE/IEC

Pin Descriptions

Pin Names Description

D

0–D3

CP Clock Pulse Input MR Q

0–Q3

Q

0–Q3

FACT is a trademark of Fairchild Semiconductor Corporation.

Data Inputs

Master Reset Input True Outputs Complement Outputs

Functional Description

The AC/ACT175 consists of four edge-triggered D-type flipflops with individual D i nputs and Q and Q

outputs. The Clock and Master Re set are common. The four f lip-flops will store the state of their individual D inputs on th e LOWto-HIGH clock (CP) transi tion, causing ind ividual Q and Q outputs to follow. A LOW input on the Master Reset (MR) will force all Q outputs LOW and Q

outputs HIGH independent of Clock or Data inputs. The AC/ACT175 is useful for general logic applic ations where a common Master R eset and Clock are acceptab le.

74AC175 • 74ACT175

Logic Diagram

Truth Table

Inputs Outputs

@ t

, MR = H@ t

n

D

n

LLH

HHL

H = HIGH Voltage Level L = LOW Voltage Level

= Bit Time before Clock Pulse

t

n

t

= Bit Time after Clock Pulse

n+1

Q

n

Q

n

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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Absolute Maximum Ratings(Note 1) Recommended Operating

Supply Voltage (VCC) −0.5V to +7.0V DC Input Diode Current (I

V

= −0.5V −20 mA

I

= VCC + 0.5V +20 mA

V

I

DC Input Voltage (V DC Output Diode Current (I

= −0.5V −20 mA

V

O

V

= VCC + 0.5V +20 mA

O

DC Output Voltage (V

)

IK

) −0.5V to VCC + 0.5V

I

)

OK

) −0.5V to VCC + 0.5V

O

DC Output Source

or Sink Current (I

DC V

or Ground Current

CC

per Output Pin (I Storage Temperature (T Junction Temperature (T

) ± 50 mA

O

or I

CC

) ± 50 mA

GND

) −65°C to +150°C

STG

)

J

PDIP 140°C

Conditions

Supply Voltage (V

AC 2.0V to 6.0V

ACT 4.5V to 5.5V Input Voltage (V Output Voltage (VO)0V to V Operating Temperature (TA) −40°C to +85°C Minimum Input Edge Rate (∆V/∆t)

AC Devices

V

from 30% to 70% of V

IN

VCC @ 3.3V, 4.5V, 5.5V 125 mV/ns Minimum Input Edge Rate (∆V/∆t)

ACT Devices

V

from 0.8V to 2.0V

IN

@ 4.5V, 5.5V 125 mV/ns

V

CC

Note 1: Absolute max imum ratings are those va lues beyond which damage to the device may occu r. The databook spe cificatio ns shou ld be met, w ithout exception, to ensure that the system de sign is relia ble over its p ower supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specif ic at ions

)

CC

)0V to V

I

CC

DC Electrical Characteristics for AC

V

Symbol Parameter

V

IH

V

IL

V

OH

V

OL

I

IN

(Note 4) I

OLD

I

OHD

I

CC

(Note 4)

Note 2: All outputs loaded; thres holds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: I

Minimum HIGH Level 3.0 1.5 2.1 2.1 V Input Voltage 4.5 2.25 3.15 3.15 V or VCC − 0.1V

Maximum LOW Level 3.0 1.5 0.9 0.9 V Input Voltage 4.5 2.25 1.35 1.35 V or VCC − 0.1V

Minimum HIGH Level 3.0 2.99 2.9 2.9 Output Voltage 4.5 4.49 4.4 4.4 V I

Maximum LOW Level 3.0 0.002 0.1 0.1 Output Voltage 4.5 0.001 0.1 0.1 V I

Maximum Input Leakage Current

Minimum Dynamic 5.5 75 mA V Output Current (Note 3) 5.5 −75 mA V Maximum Quiescent

Supply Current

and ICC @ 3.0V are guaranteed to be less than or e qual to the respective lim it @ 5. 5V VCC.

IN

CC

(V) Typ Guaranteed Limits

5.5 2.75 3.85 3.85

5.5 2.75 1.65 1.65

5.5 5.49 5.4 5.4

3.0 2.56 2.46 IOH = −12 mA

4.5 3.86 3.76 V I

5.5 4.86 4.76 I

5.5 0.001 0.1 0.1

3.0 0.36 0.44 IOL = 12 mA

4.5 0.36 0.44 V IOL = 24 mA

5.5 0.36 0.44 IOL = 24 mA (Note 2)

5.5 ±0.1 ± 1.0 µAVI = VCC, GND

5.5 4.0 40.0 µAVIN = VCC or GND

TA = +25°CT

= −40°C to +85°C

A

Units Conditions

VIN = VIL or V

= 0.1V

OUT

= 0.1V

OUT

= −50 µA

OUT

IH

= −24 mA

OH

= −24 mA (Note 2)

OH

= 50 µA

OUT

IH

= 1.65V Max

OLD

= 3.85V Min

OHD

74AC175 • 74ACT175

CC CC

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DC Electrical Characteristics for ACT

V

Symbol Parameter

V

Minimum HIGH Level 4.5 1.5 2.0 2.0

IH

CC

(V) Typ Guaranteed Limits

Input Voltage 5.5 1.5 2.0 2.0 or VCC − 0.1V

V

Maximum LOW Level 4.5 1.5 0.8 0.8

IL

Input Voltage 5.5 1.5 0.8 0.8 or V

V

74AC175 • 74ACT175

Minimum HIGH Level 4.5 4.49 4.4 4.4

OH

Output Voltage 5.5 5.49 5.4 5.4

4.5 3.86 3.76 V IOH = −24 mA

5.5 4.86 4.76 I

V

Maximum LOW Level 4.5 0.001 0.1 0.1

OL

Output Voltage 5.5 0.001 0.1 0.1

4.5 0.36 0.44 V IOL = 24 mA

5.5 0.36 0.44 IOL = 24 mA (Note 5)

I

IN

I

CCT

I

OLD

I I

Note 5: All outputs loaded; thresholds on input associated with output under test. Note 6: Maximum test dura tio n 2. 0 ms, one output loaded at a time.

OHD CC

Maximum Input Leakage Current 5.5 ±0.1 ± 1.0 µAVI = VCC, GND Maximum ICC/Input 5.5 0.6 1.5 mA VI = VCC − 2.1V Minimum Dynamic 5.5 75 mA V Output Current(Note 6) 5.5 −75 mA V Maximum Quiescent Supply Current or GND

5.5 4.0 40.0 µA

AC Electrical Characteristics for AC

Symbol Parameter (V)

f

MAX

Maximum Clock 3.3 149 214 139 Frequency 5.0 187 244 187

t

Note 7: Voltage Range 3.3 is 3.3V ± 0.3V

Propagation Delay 3.3 2.0 9.5 12.0 2.0 13.5

PLH

CP to Qn or Q Propagation Delay 3.3 2.5 8.5 13.0 2.0 14.5

PHL

CP to Qn or Q Propagation Delay 3.3 3.0 7.5 12.5 2.5 13.5

PLH

MR to Q

n

Propagation Delay 3.3 3.0 8.5 11.0 2.5 12.5

PHL

MR to Q

n

Voltage Range 5.0 is 5.0V ± 0.5V

n

V

(Note 7) Min Typ Max Min Max

5.0 1.5 7.0 9.0 1.0 9.5

5.0 1.5 6.0 9.5 1.5 10.5

5.0 2.0 5.5 9.0 1.5 10.0

5.0 2.0 6.0 8.5 1.5 9.0

TA = +25°CTA = −40°C to +85°C

CC

TA = +25°CT CL = 50 pF CL = 50 pF

Units Conditions

V

= 0.1V

OUT

V

= 0.1V

OUT

V

VI

= −40°C to +85°C

A

− 0.1V

CC

= −50 µA

OUT

VIN = VIL or V

= −24 mA (Note 5)

OH

= 50 µA

OUT

VIN = VIL or V

= 1.65V Max

OLD

= 3.85V Min

OHD

VIN = V

CC

IH

Units

MHz

ns

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AC Operating Requirements for AC

Symbol Parameter (V)

t

S

t

H

t

W

Setup Time, HIGH or LOW 3.3 2.0 4.5 4.5

to CP 5.0 1.0 3.0 3.0

D

n

Hold Time, HIGH or LOW 3.3 1.0 1.0 1.0 D

to CP 5.0 1.0 1.0 1.0

n

CP Pulse Width 3.3 2.5 4.5 4.5 HIGH or LOW 5.0 2.0 3.5 3.5

t

W

REC

MR Pulse Width, LOW

Recovery Time 3.3 −2.0 0 0 MR to CP

Note 8: Voltage Range 3.3 is 3.3V ± 0.3V

Voltage Range 5.0 is 5.0V ± 0.5V

V

(Note 8) Typ Guaranteed Minimum

3.3 2.5 4.5 5.0

5.0 2.0 3.5 3.5

5.0 −1.0 0 0

AC Electrical Characteristics for ACT

Symbol Parameter (V)

f

MAX

Maximum Clock Frequency

t

PLH

t

PHL

t

PLH

t

PHL

Note 9: Voltage Range 5.0 is 5.0V ± 0.5V

Propagation Delay CP to Qn or Q

n

Propagation Delay CP to Qn or Q

n

Propagation Delay MR to Q

n

Propagation Delay MR

to Q

n

V

CC

(Note 9) Min Typ Max Min Max

5.0 175 236 145 MHz

5.0 2.0 6.0 10.0 1.5 11.0 ns

5.0 2.0 7.0 11.0 1.5 12.0 ns

5.0 2.0 6.0 9.5 1.5 10.5 ns

5.0 2.0 5.5 9.5 1.5 10.5 ns

CC

TA = +25°CT C

= 50 pF CL = 50 pF

L

TA = +25°CT CL = 50 pF CL = 50 pF

= −40°C to +85°C

A

= −40°C to +85°C

A

74AC175 • 74ACT175

Units

ns

Units

AC Operating Requirements for ACT

V

CC

Symbol Parameter (V)

(Note 10) Typ Guaranteed Minimum

(H) Setup Time 5.0 3.0 2.0 2.0

t

S

tS (L) Dn to CP 3.0 2.5 2.5 t

H

t

W

t

W

t

rec

Note 10: Voltage Ran ge 5.0 is 5.0V ± 0.5V

Hold Time, HIGH or LOW Dn to CP CP Pulse Width HIGH or LOW

MR Pulse Width, LOW Recovery Time, MR to CP

5.001.0 1.0 ns

5.0 4.0 3.0 3 .5 ns

5.0 4.0 3.0 4 .0 ns

5.0 0 0 0 ns

TA = +25°CT

= −40°C to +85°C

A

CL = 50 pF CL = 50 pF

Capacitance

Symbol Parameter Typ Units Conditions

C

IN

C

PD

Input Capacitance 4.5 pF VCC = OPEN Power Dissipation Capacitance 45.0 pF VCC = 5.0V

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Units

ns

Physical Dimensions inches (millimeters) unless otherwise noted

74AC175 • 74ACT175

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS -120, 0.150” Narrow Body

Package Number M16A

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

74AC175 • 74ACT175

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M16D

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

74AC175 • 74ACT175

16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

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Package Number MTC16

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

74AC175 • 74ACT175 Quad D-Typ e Flip- Flop

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Fairchild does not assume any responsibility for use of any circuitry described , no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are dev ic es or syste ms which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provide d in the l abe ling, can be reasonably expected to result in a significant injury to the user.

Package Number N16E

2. A critical compo nent in any com ponen t of a life s upp ort device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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