Page 1
54AC16620, 74AC16620
16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS239A – JULY 1990 – REVISED APRIL 1996
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Members of the Texas Instruments
Widebus
Family
D
3-State Outputs Drive Bus Lines Directly
D
Flow-Through Architecture Optimizes
PCB Layout
D
Distributed VCC and GND Pin
Configurations Minimize High-Speed
Switching Noise
D
EPIC
(Enhanced-Performance Implanted
CMOS) 1-µm Process
D
500-mA Typical Latch-Up Immunity at
125°C
D
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Packages Using
25-mil Center-to-Center Pin Spacings and
380-mil Fine-Pitch Ceramic Flat (WD)
Packages Using 25-mil Center-to-Center
Pin Spacings
description
The ’AC16620 are inverting 16-bit transceivers
designed for asynchronous communication
between data buses. The control-function
implementation allows for maximum flexibility in
timing.
These devices can be used as two 8-bit
transceivers or one 16-bit transceiver. They allow
data transmission from the A bus to the B bus or
from the B bus to the A bus, depending on the logic
level at the complementary output-enable (OEAB
or OEBA
) inputs. The output-enable inputs can be
used to disable the device so that the buses are
effectively isolated.
The dual-enable configuration gives the transceiver the capability to store data by simultaneously enabling
OEAB and OEBA. Each output reinforces its input in this transceiver configuration. Thus, when both control
inputs are enabled and all other data sources to the two sets of bus lines are at high impedance, the bus lines
remain at their last states.
The 74AC16620 is packaged in TI’s shrink small-outline package, which provides twice the I/O pin count and
functionality of standard small-outline packages in the same printed-circuit-board area.
The 54AC16620 is characterized for operation over the full military temperature range of –55°C to 125°C. The
74AC16620 is characterized for operation from –40°C to 85°C.
Copyright 1996, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1OEAB
1B1
1B2
GND
1B3
1B4
V
CC
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
V
CC
2B5
2B6
GND
2B7
2B8
2OEAB
1OEBA
1A1
1A2
GND
1A3
1A4
V
CC
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
V
CC
2A5
2A6
GND
2A7
2A8
2OEBA
54AC16620 . . . WD PACKAGE
74AC16620 . . . DL PACKAGE
(TOP VIEW)
Page 2
54AC16620, 74AC16620
16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS239A – JULY 1990 – REVISED APRIL 1996
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
(each 8-bit section)
INPUTS
OEBA OEAB
OPERATION
L L B data to A bus
L H
B data to A bus,
A
data to B bus
H L Isolation
H H A data to B bus
logic symbol
†
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2OEBA
1OEBA
EN1
48
EN2
1
1OEAB
1A2
46
1A3
44
1A4
43
1A5
41
1A6
40
1A7
38
1A8
37
1A1
47
1B1
2
1B2
3
1B3
5
1B4
6
1B5
8
1B6
9
1B7
11
1B8
12
EN3
25
EN4
24
2OEAB
1
112
2A2
35
2A3
33
2A4
32
2A5
30
2A6
29
2A7
27
2A8
26
2A1
36
2B1
13
2B2
14
2B3
16
2B4
17
2B5
19
2B6
20
2B7
22
2B8
23
1
134
Page 3
54AC16620, 74AC16620
16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS239A – JULY 1990 – REVISED APRIL 1996
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
2B1
13
2A1
2OEAB
2OEBA
36
24
25
1B1
2
1A1
1OEAB
1OEBA
47
1
48
To Seven Other Channels
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±400 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum power dissipation at T
A
= 55°C (in still air) (see Note 2): DL package 1.2 W. . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils.
Page 4
54AC16620, 74AC16620
16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS239A – JULY 1990 – REVISED APRIL 1996
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Note 2)
54AC16620 74AC16620
MIN NOM MAX MIN NOM MAX
UNIT
V
CC
Supply voltage 3 5 5.5 3 5 5.5 V
VCC = 3 V 2.1 2.1
V
IH
High-level input voltage
VCC = 4.5 V
3.15 3.15
V
VCC = 5.5 V 3.85 3.85
VCC = 3 V 0.9 0.9
V
IL
Low-level input voltage
VCC = 4.5 V
1.35 1.35
V
VCC = 5.5 V 1.65 1.65
V
I
Input voltage 0 V
CC
0 V
CC
V
V
O
Output voltage 0 V
CC
0 V
CC
V
VCC = 3 V –4 –4
I
OH
High-level output current
VCC = 4.5 V
–24 –24
mA
VCC = 5.5 V –24 –24
VCC = 3 V 12 12
I
OL
Low-level output current
VCC = 4.5 V
24 24
mA
VCC = 5.5 V 24 24
∆t/∆v Input transition rise or fall rate 0 10 0 10 ns/V
T
A
Operating free-air temperature –55 125 –40 85 °C
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C 54AC16620 74AC16620
PARAMETER
TEST CONDITIONS
V
CC
MIN TYP MAX MIN MAX MIN MAX
UNIT
3 V 2.9 2.9 2.9
IOH = –50 µA
4.5 V 4.4 4.4 4.4
5.5 V 5.4 5.4 5.4
V
OH
IOH = –4 mA 3 V 2.58 2.48 2.48
V
4.5 V 3.94 3.8 3.8
I
OH
= –24
mA
5.5 V 4.94 4.8 4.8
IOH = –75 mA
†
5.5 V 3.85 3.85
3 V 0.1 0.1 0.1
IOL = 50 µA
4.5 V 0.1 0.1 0.1
5.5 V 0.1 0.1 0.1
V
OL
IOL = 12 mA 3 V 0.36 0.44 0.44
V
4.5 V 0.36 0.44 0.44
I
OL
= 24
mA
5.5 V 0.36 0.44 0.44
IOL = 75 mA
†
5.5 V 1.65 1.65
I
I
Control inputs VI = VCC or GND 5.5 V ±0.1 ±1 ±1 µA
I
OZ
‡
A or B ports VO = VCC or GND 5.5 V ±0.5 ±5 ±5 µA
I
CC
VI = VCC or GND, IO = 0 5.5 V 8 80 80 µA
C
i
Control inputs VI = VCC or GND 5 V 4.5 pF
C
io
A or B ports VO = VCC or GND 5 V 16 pF
†
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
‡
For I/O ports, the parameter IOZ includes the input leakage current.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
Page 5
54AC16620, 74AC16620
16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS239A – JULY 1990 – REVISED APRIL 1996
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range,
V
CC
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
FROM TO
TA = 25°C 54AC16620 74AC16620
PARAMETER
(INPUT) (OUTPUT)
MIN TYP MAX MIN MAX MIN MAX
UNIT
t
PLH
2.7 6.1 8.7 2.7 9.7 2.7 9.7
t
PHL
A or B
B or A
3.9 7.9 10.6 3.9 11.7 3.9 11.7
ns
t
PZH
3.2 7.1 10 3.2 11.2 3.2 11.2
t
PZL
OEBA
A
4.5 11.1 13.5 4.5 15 4.5 15
ns
t
PHZ
5.3 7.4 9.5 5.3 10.2 5.3 10.2
t
PLZ
OEBA
A
4.6 7 9.2 4.6 9.8 4.6 9.8
ns
t
PZH
3.1 6.7 9.5 3.1 10.7 3.1 10.7
t
PZL
OEAB
B
4.4 9.6 13 4.4 14.5 4.4 14.5
ns
t
PHZ
5 7.1 9.3 5 9.8 5 9.8
t
PLZ
OEAB
B
4.4 6.8 8.9 4.4 9.4 4.4 9.4
ns
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
FROM TO
TA = 25°C 54AC16620 74AC16620
PARAMETER
(INPUT) (OUTPUT)
MIN TYP MAX MIN MAX MIN MAX
UNIT
t
PLH
2.1 3.9 6.1 2.1 6.8 2.1 6.8
t
PHL
A or B
B or A
3.1 4.9 7.3 3.1 8.2 3.1 8.2
ns
t
PZH
2.2 4.3 6.8 2.2 7.6 2.2 7.6
t
PZL
OEBA
A
3.3 5.5 8.4 3.3 9.4 3.3 9.4
ns
t
PHZ
4.9 6.6 8.6 4.9 9.2 4.9 9.2
t
PLZ
OEBA
A
4.1 5.8 7.8 4.1 8.3 4.1 8.3
ns
t
PZH
2.2 4.2 6.5 2.2 7.3 2.2 7.3
t
PZL
OEAB
B
3.4 5.4 8.1 3.4 9.1 3.4 9.1
ns
t
PHZ
4.6 6.4 8.5 4.6 9 4.6 9
t
PLZ
OEAB
B
4.1 5.6 7.6 4.1 8 4.1 8
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
p
p
p
Outputs enabled
p
49
p
CpdPower dissipation capacitance per transceiver
Outputs disabled
C
L
= 50 pF,
f
= 1 MHz
6
pF
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
Page 6
54AC16620, 74AC16620
16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS239A – JULY 1990 – REVISED APRIL 1996
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
50% V
CC
t
PLH
t
PHL
t
PHL
t
PLH
V
OH
V
OH
V
OL
V
OL
50% 50%
V
CC
0 V
50% V
CC
50% V
CC
Input
Out-of-Phase
Output
In-Phase
Output
50% V
CC
VOLTAGE WAVEFORMS
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
2 × V
CC
500 Ω
500 Ω
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
CC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
V
OL
V
OH
t
PZL
t
PZH
t
PLZ
t
PHZ
50%
50%
[
V
CC
0 V
50% V
CC
20% V
CC
50% V
CC
80% V
CC
[
0 V
V
CC
GND
Open
VOLTAGE WAVEFORMS
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open
2 × V
CC
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
Page 7
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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Copyright 1998, Texas Instruments Incorporated
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