The 74AC14 is an advanced high-speed CMOS
HEX SCHMITT TRIGGER INVERTER fabricated
with sub-micron silicon gate and double-layer
metal wiring C
2
MOS technology.
The internal circuit is composed of 3 stages
including buffer output , which enables high noise
immunity and stable output.
TSSOPDIPSOP
ORDER CODES
PACKAGETUBET & R
DIP74AC14B
SOP74AC14M74AC14MTR
TSSOP74AC14TTR
This together with its schmitt trigger function
allows it to be used on line receivers with slow
rise/fall input signals.
All inputs and outputs are equipped with
protection circuits against stat ic discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
1/8July 2001
Page 2
74AC14
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN NoSYMBOLNAME AND FUNCTION
1, 3, 5, 9, 1 1,
13
2, 4, 6, 8, 10,
12
7GNDGround (0V)
14
TRUTH TABLE
ABSOLUTE MAXIMUM RATINGS
SymbolParameterValueUnit
V
V
V
I
I
OK
I
I
or I
CC
T
T
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
Supply Voltage
CC
DC Input Voltage-0.5 to VCC + 0.5
I
DC Output Voltage-0.5 to VCC + 0.5
O
DC Input Diode Current
IK
DC Output Diode Current
DC Output Current
O
DC VCC or Ground Current
GND
Storage Temperature
stg
Lead Temperature (10 sec)
L
1A to 6AData Inputs
1Y to 6YData Outputs
V
CC
Positive Supply Voltage
AY
LH
HL
-0.5 to +7V
V
V
± 20mA
± 20mA
± 50mA
± 300mA
-65 to +150°C
300°C
RECOMMENDED OPERATING CONDITIONS
SymbolParameterValueUnit
V
V
V
T
2/8
Supply Voltage
CC
Input Voltage0 to V
I
Output Voltage0 to V
O
Operating Temperature
op
2 to 6V
CC
CC
-55 to 125°C
V
V
Page 3
DC SPECIFICATIONS
Test ConditionValue
T
SymbolParameter
V
CC
(V)
V
High Level Input
t+
Voltage
3.0
T
=Worst Case
A
5.53.93.93.9
V
t-
Low Level Input
Voltage
3.0
T
=Worst Case
A
5.51.11.11.1
Hysteresis Voltage3.0
V
h
T
=Worst Case
A
5.50.51.60.51.61.6
V
High Level Output
OH
Voltage
3.0
4.5
5.5
3.0
4.5
5.5
V
Low Level Output
OL
Voltage
3.0
4.5
5.5
3.0
4.5
5.5
I
Input Leakage Cur-
I
rent
I
I
OLD
I
OHD
1) Maxim um test duration 2ms, one output loaded at tim e
2) Incid ent wave switching is guaranteed on transmission l i nes with impe dances as low as 50Ω
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