Datasheet 74AC125SJX, 74AC125SJ, 74AC125SCX, 74AC125SC, 74AC125PC Datasheet (Fairchild Semiconductor)

© 1999 Fairchild Semiconductor Corporation DS010692 www.fairchildsemi.com

March 1990
Revised November 1999

74AC125 • 74ACT125 Quad Buffer with 3-STATE Outputs

74AC125 • 74ACT125
Quad Buffer with 3-STATE Outputs

General Description

The AC/ACT125 conta ins four independent non-invert ing
buffers with 3-STATE outputs.

Features

■ ICC reduced by 50%

■ Outputs source/sink 24 mA

■ ACT125 has TTL-compatible outputs

Ordering Code:

Device also available in Tape and Reel. Specify by appending s uffix let te r “X” to the ordering code.

Logic Symbol

IEEE/IEC

Pin Descriptions

Connection Diagram

Function Table

H = HIGH Voltage Level
L = LOW Voltage Level
Z = HIGH Impedance
X = Immaterial

FACT is a trademark of Fairchild Semiconductor Corporation.

Order Number Package Number Package Description

74AC125SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body
74AC125SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC125MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC125PC N14A 14-Lead Plastic Dual-in-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
74ACT125SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body
74ACT125SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT125MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT125PC N14A 14-Lead Plastic Dual-in-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Pin Names Description

A

n

, B

n

Inputs

O

n

Outputs

Inputs Output

A

n

B

n

O

n

LL L
LH H
HX Z

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74AC125 • 74ACT125

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: Absolute maximum ratings are those values beyond which damage

to the device may occur. The databook specifications should be met, with­out exception, to ensure that the system design is reliable over its power
supply, temperature, and ou tput/inp ut loadi ng varia bles. Fairchild does no t
recommend operat ion of FACT circuits outside da t abook specifications.

DC Electrical Characteristics for AC

Note 2: All outputs loaded; thresholds on input assoc iat ed with output under tes t.
Note 3: Maximum test duratio n 2. 0 ms, one output loaded at a time.
Note 4: Note: I

IN

and ICC@ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.

Supply Voltage (VCC) −0.5V to +7.0V
DC Input Diode Current (I

K

)

V

I

= −0.5V −20 mA

V

I

= VCC + 0.5V +20 mA

DC Input Voltage (V

I

) −0.5V to VCC + 0.5V

DC Output Diode Current (I

OK

)

V

O

= −0.5V −20 mA

V

O

= VCC + 0.5V +20 mA

DC Output Voltage (V

O

) −0.5V to VCC + 0.5V

DC Output Source

or Sink Current (I

O

) ±50 mA

DC V

CC

or Ground Current

per Output Pin (I

CC

or I

GND

) ±50 mA

Storage Temperature (T

STG

) −65°C to +150°C

Junction Temperature (T

J

)

PDIP 140°C

Supply Voltage (V

CC

)
AC 2.0V to 6.0V
ACT 4.5V to 5.5V

Input Voltage (V

I

) 0V to V

CC

Output Voltage (VO) 0V to V

CC

Operating Temperature (TA) −40°C to +85°C
Minimum Input Edge Rate (∆V/∆t)

AC Devices
V

IN

from 30% to 70% of V

CC

VCC @ 3.3V, 4.5V, 5.5V 125 mV/ns

Minimum Input Edge Rate (∆V/∆t)

ACT Devices
V

IN

from 0.8V to 2.0V

V

CC

@ 4.5V, 5.5V 125 mV/ns

Symbol Parameter

V

CC

TA = +25°CTA = −40°C to +85°C

Units Conditions

(V) Typ Guaranteed Limits

V

IH

Minimum HIGH Level 3.0 1.5 2.1 2.1 V

OUT

= 0.1V

Input Voltage 4.5 2.25 3.15 3.15 V or VCC − 0.1V

5.5 2.75 3.85 3.85

V

IL

Maximum LOW Level 3.0 1.5 0.9 0.9 V

OUT

= 0.1V

Input Voltage 4.5 2.25 1.35 1.35 V or VCC − 0.1V

5.5 2.75 1.65 1.65

V

OH

Minimum HIGH Level 3.0 2.99 2.9 2.9
Output Voltage 4.5 4.49 4.4 4.4 V I

OUT

= −50 µA

5.5 5.49 5.4 5.4
VIN = VIL or V

IH

3.0 2.56 2.46 IOH = −12 mA

4.5 3.86 3.76 V I

OH

= −24 mA

5.5 4.86 4.76 I

OH

= −24 mA (Note 2)

V

OL

Maximum LOW Level 3.0 0.002 0.1 0.1
Output Voltage 4.5 0.001 0.1 0.1 V I

OUT

= 50 µA

5.5 0.001 0.1 0.1
VIN = VIL or V

IH

3.0 0.36 0.44 IOL = 12 mA

4.5 0.36 0.44 V IOL =24 mA

5.5 0.36 0.44 IOL = 24 mA (Note 2)

IIN (Note 4) Maximum Input Leakage Current 5.5 ± 0.1 ± 1.0 µAVI = VCC, GND
I

OZ

Maximum 3-STATE Current VI (OE) = VIL, V

IH

5.5 ± 0.25 ± 2.5 µAVI = VCC, V

GND

VO = VCC, GND

I

OLD

Minimum Dynamic 5.5 75 mA V

OLD

= 1.65V Max

I

OHD

Output Current (Note 3) 5.5 −75 mA V

OHD

= 3.85V Min

I

CC

(Note 4) Maximum Quiescent Supply Current 5.5 4.0 40.0 µAVIN = VCC or GND

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74AC125 • 74ACT125

DC Electrical Characteristics for ACT

Note 5: All outputs loaded; thres holds on input associate d w it h output under test.
Note 6: Maximum test duration 2.0 ms, one output loaded at a time.
Note 7: May be measured per the J ED EC Alternate Metho d.

Symbol Parameter

V

CC

TA = +25°CTA = −40°C to +85°C

Units Conditions

(V) Typ Guaranteed Limits

V

IH

Minimum HIGH Level 4.5 1.5 2.0 2.0

V

V

OUT

= 0.1V

Input Voltage 5.5 1.5 2.0 2.0 or VCC − 0.1V

V

IL

Maximum LOW Level 4.5 1.5 0.8 0.8

V

V

OUT

= 0.1V

Input Voltage 5.5 1.5 0.8 0.8 or V

CC

− 0.1V

V

OH

Minimum HIGH Level 4.5 4.49 4.4 4.4

VI

OUT

= −50 µA

Output Voltage 5.5 5.49 5.4 5.4

VIN = VIL or V

IH

4.5 3.86 3.76
V

IOH = −24 mA

5.5 4.86 4.76 I

OH

= −24 mA (Note 5)

V

OL

Maximum LOW Level 4.5 0.001 0.1 0.1

VI

OUT

= 50 µA

Output Voltage 5.5 0.001 0.1 0.1

VIN = VIL or V

IH

4.5 0.36 0.44
V

IOL = 24 mA

5.5 0.36 0.44 IOL = 24 mA (Note 5)

I

IN

Maximum Input

5.5 ±0.1 ±1.0 µAVI = VCC, GND

Leakage Current

I

OZ

Maximum 3- STATE

5.5 ±0.5 ±5.0 µA

VI = VIL, V

IH

Current VO = VCC, GND

I

CCT

Maximum ICC/Input 5.5 0.6 1.5 mA VI = VCC − 2.1V (Note 7)

I

OLD

Minimum Dynamic 5.5 75 mA V

OLD

= 1.65V Max

I

OHD

Output Current (Note 6) 5.5 −75 mA V

OHD

= 3.85V Min

I

CC

Maximum Quiescent

5.5 4.0 40.0 µA

VIN = V

CC

Supply Current or GND

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74AC125 • 74ACT125

AC Electrical Characteristics for AC

Note 8: Voltage Range 3.3 is 3.3V ± 0.3V

Voltage Range 5.0 is 5.0V ± 0.5V

AC Electrical Characteristics for ACT

Note 9: Voltage Range 5.0 is 5.0V ± 0.5V

Capacitance

V

CC

TA = +25°CT

A

= −40°C to +85°C

Symbol Parameter (V)

C

L

= 50 pF CL = 50 pF

Units

(Note 8) Min Typ Max Min Max

t

PLH

Propagation Delay 3.3 1.0 6.5 9.0 1.0 10.0

ns

Data to Output 5.0 1.0 5.5 7.0 1.0 7.5

t

PHL

Propagation Delay 3.3 1.0 6.5 9.0 1.0 10.0

ns

Data to Output 5.0 1.0 5.0 7.0 1.0 7.5

t

PZH

Output Enable Time 3.3 1.0 6.0 10.5 1.0 11.0

ns

5.0 1.0 5.0 7.0 1.0 8.0

t

PZL

Output Enable Time 3.3 1.0 7.5 10.0 1.0 11.0

ns

5.0 1.0 5.5 8.0 1.0 8.5

t

PHZ

Output Disable Time 3.3 1.0 7.5 10.0 1.0 10.5

ns

5.0 1.0 6.5 9.0 1.0 9.5

t

PLZ

Output Disable Time 3.3 1.0 7.5 10.5 1.0 11.5

ns

5.0 1.0 6.5 9.0 1.0 9.5

V

CC

TA = +25°CT

A

= −40°C to +85°C

Symbol Parameter (V)

CL = 50 pF CL = 50 pF

Units

(Note 9) Min Typ Max Min Max

t

PLH

Propagation Delay

5.0 1.0 6.5 9.0 1.0 10.0 ns

Data to Output

t

PHL

Propagation Delay

5.0 1.0 7.0 9.0 1.0 10.0 ns

Data to Output

t

PZH

Output Enable Time 5.0 1.0 6.0 8 .5 1.0 9.5 ns

t

PZL

Output Enable Time 5.0 1.0 7.0 9.5 1.0 10.5 ns

t

PHZ

Output Disable Time 5.0 1.0 7.0 9.5 1.0 10.5 ns

t

PLZ

Output Disable Time 5.0 1.0 7.5 10.0 1.0 10.5 ns

Symbol Parameter AC/ACT Units Conditions

Typ

C

IN

Input Capacitance 4.5 pF VCC = OPEN

C

PD

Power Dissipation Capacitance 45.0 pF VCC = 5.0V

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74AC125 • 74ACT125

Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body

Package Number M14A

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74AC125 • 74ACT125

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M14D

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74AC125 • 74ACT125

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Thin Shrink Sm all Ou tline Pa ck age (TS SO P), JE DE C MO-153, 4.4mm Wide

Package Number MTC14

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74AC125 • 74ACT125 Quad Buffer with 3-STATE Outputs

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-in-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Package Number N14A

Fairchild does not assume any responsibility for use of any circuitr y described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea­sonably expected to result in a significant inju ry to the
user.

2. A critical component i n any compon ent of a lif e supp ort
device or system whose failure t o perform can be rea­sonably expected to ca use the failure of the life supp ort
device or system, or to affect its safety or effectiveness.

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