Page 1
INTEGRATED CIRCUITS
74ABT16273
74ABTH16273
16-bit D-type flip-flop
Product specification
Supersedes data of 1995 Sep 28
IC23 Data Handbook
1998 Feb 27
Page 2
Philips Semiconductors Product specification
Quiescent su ly current
16-bit D-type flip-flop
FEA TURES
•16-bit D-type edge triggered flip-flops
•Output capability: +64mA/–32mA
•TTL input and output switching levels
•Live insertion/extraction permitted
•Power-up reset
•74ABTH16273 incorporates bus-hold data inputs which eliminate
the need for external pull-up resistors to hold unused inputs
•Latch-up protection exceeds 500mA per JEDEC Std 17
•ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
QUICK REFERENCE DATA
SYMBOL PARAMETER
t
PLH
t
PHL
C
I
CCH
I
CCL
IN
Propagation delay
An to Bn or Bn to An
Input capacitance VI = 0V or V
pp
74ABT16273
74ABTH16273
DESCRIPTION
The 74ABT16273 high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
This part is a 16-bit edge triggered D-type flip-flop with non-inverting
high drive outputs. This device can be used as two 8-bit flip-flops or
one 16-bit flip-flop. When the clock (CP) goes High, the data on the
D inputs is stored and the Q outputs display the stored data.
This device also features a master reset (MR
flip-flops to the Low state when MR
is set to the Low state.
Two options are available, 74ABT16273 which does not have the
bus-hold feature and 74ABTH16273 which incorporates the
bus-hold feature.
CONDITIONS
T
= 25°C; GND = 0V
amb
CL = 50pF;
VCC = 5.0V
CC
Outputs High; VCC = 5.5V 200 µA
Outputs low; VCC = 5.5V 8 mA
) that resets all
TYPICAL UNIT
2.5
2.0
ns
4 pF
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER
48-Pin Plastic SSOP Type III –40°C to +85°C 74ABT16273 DL BT16273 DL SOT370-1
48-Pin Plastic TSSOP Type II –40°C to +85°C 74ABT16273 DGG BT16273 DGG SOT362-1
48-Pin Plastic SSOP Type III –40°C to +85°C 74ABTH16273 DL BH16273 DL SOT370-1
48-Pin Plastic TSSOP Type II –40°C to +85°C 74ABTH16273 DGG BH16273 DGG SOT362-1
LOGIC SYMBOL
1
1D0 1D1 1D2 1D3
CP
MR
1Q0 1Q1 1Q2651Q3
CP
MR
2Q0 2Q1 2Q2 2Q3
48
25
24
47 46 44 43
32
36 35 33 32
2D02D21 2D2 2D3
41 40 38 37
1D4 1D5 1D6 1D7
1Q4 1Q5 1Q6
30 29 27 26
2D4 2D5 2D6 2D7
2Q4 2Q5 2Q6 2Q7
1Q7
98
1211
PIN DESCRIPTION
PIN NUMBER SYMBOL
1, 24 1MR, 2MR
2, 3, 5, 6, 8, 9, 11, 12,13,
14, 16, 17, 19, 20, 22, 23
47, 46, 44, 43, 41, 40, 38, 37,
36, 35, 33, 32, 30, 29, 27, 26
1Q0-1Q7
2Q0-2Q7
1D0-1D7
2D0-2D7
25, 48 1CP, 2CP
4, 10, 15, 21, 28, 34, 39, 45 GND Ground (0V)
7, 18, 31, 42 V
CC
NAME AND
FUNCTION
Master reset input
(active-Low)
Data outputs
Data inputs
Clock pulse input
(active rising edge)
Positive supply
voltage
1998 Feb 27 853-1793 19027
1413 1716
2019 2322
SH00052
2
Page 3
Philips Semiconductors Product specification
16-bit D-type flip-flop
LOGIC SYMBOL (IEEE/IEC)
1
1MR
48
CP
24
2MR
25
2CP
47
1D0
46
1D1
44
1D2
43
1D3
41
1D4
40
1D5
38
1D6
37
1D7
36
2D0
35
2D1
33
2D2
32
2D3
30
2D4
29
2D5
27
2D6
26
2D7
FUNCTION TABLE
Inputs Output
nMR nCP nDX nQ0-nQ7
L X X L Reset (clear)
H ↑ h H Load “1”
H ↑ I L Load “0”
H L X Q
H = High voltage level
h = high voltage level one set-up time prior to the Low-to-High
clock transition
L = Low voltage level
I = Low voltage level one set-up time prior to the Low-to-High
clock transition
X = Don’t care
↑ = Low-to-High clock transition
0= Output as it was
Q
R1
C1
R2
C2
1 ∇1D
2D
2 ∇
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
SH00053
1Q0
!Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
operating
mode
0
Retain state
PIN CONFIGURATION
1
1MR
2
1Q0
!Q1
3
GND
4
1Q2
5
1Q3
6
7
V
CC
8
1Q4
1Q5
9
GND
10
1Q6
11
1Q7
12
2Q0
13
2Q1
14
GND
15
16
2Q2
2Q3
17
18
V
CC
2Q4
19
20
2Q5
21
GND
22
2Q6
23
2Q7
24
2MR
74ABT16273
74ABTH16273
48
CP
47
1D0
1D1
46
GND
45
1D2
44
1D3
43
42
V
CC
41
1D4
1D5
40
GND
39
1D6
38
1D7
37
2D0
36
2D1
35
GND
34
33
2D2
32
2D3
31
V
CC
2D4
30
29
2D5
28
GND
27
2D6
26
2D7
25
2CP
SH00054
1998 Feb 27
3
Page 4
Philips Semiconductors Product specification
I
DC output current
mA
16-bit D-type flip-flop
LOGIC DIAGRAM
nD1
Q
nQ0
D
CP
R
D
nCP
nMR
nD0
D
CP
R
D
n = 1 or 2
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
V
CC
I
IK
V
I
OK
OUT
OUT
T
stg
DC supply voltage –0.5 to –7.0 V
DC input diode current VI < 0 –18 mA
DC input voltage
I
DC output diode current VO < 0 –50 mA
DC output voltage
p
Storage temperature range –65 to +150 °C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
PARAMETER CONDITIONS RATING UNIT
3
3
nD2
Q
nQ1 nQ2 nQ3 nQ4 nQ5 nQ6 nQ7
D
CP
R
D
nD3
Q
D
CP
R
D
nD4
Q
D
CP
R
D
nD5
Q
Q
D
CP
R
D
1, 2
Output in Off or High state –0.5 to +5.5 V
Output in Low state 128
Output in High state –64
74ABTH16273
nD6
D
CP
R
D
–1.2 to +7.0 V
nD7
Q
D
CP
R
Q
D
SH00055
74ABT16273
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER LIMITS UNIT
1998 Feb 27
MIN MAX
V
CC
V
V
V
I
OH
I
OL
DC supply voltage 4.5 5.5 V
Input voltage 0 V
I
High-level input voltage 2.0 V
IH
Input voltage 0.8 V
IL
High-level output current –32 mA
Low-level output current 64 mA
CC
V
∆t/∆v Input transition rise or fall rate; Outputs enabled 0 10 ns/V
T
amb
Operating free-air temperature range –40 +85 °C
4
Page 5
Philips Semiconductors Product specification
I
t
I
g
V
V
V
GND
±0.1±1±1µA
I
74ABT16273
CC I CC
µ
In ut leakage current
Data pins
4
Quiescent supply current
mA
16-bit D-type flip-flop
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL PARAMETER TEST CONDITIONS Temp = +25°C
MIN TYP MAX MIN MAX
V
V
V
V
I
HOLD
I
OFF
I
CEX
I
CCH
I
CCL
∆I
∆I
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
4. This is the bus hold overdrive current required to force the input to the opposite logic state.
Input clamp voltage VCC = 4.5V; IIK = –18mA 0.9 –1.2 –1.2 V
IK
VCC = 4.5V; IOH = –3mA; VI = VIL or V
High-level output voltage
OH
VCC = 5.0V; IOH = –3mA; VI = VIL or V
VCC = 4.5V; IOH = –32mA; VIL or V
Low-level output voltage VCC = 4.5V; IOL = 64mA; VI = VIL or V
OL
RST
I
Power-up output
3
voltage
nput leakage curren
VCC = 5.5V; IO = 1mA; VI = GND or V
;
= 5.5V;
CC
=
I
CC
VCC = 5.5V; VI = VCC or GND
I
I
p
74ABTH16273
VCC = 5.5V; VI = V
CC
VCC = 5.5V; VI = 0
IH
IH
IH
IH
CC
or
Control
pins
p
2.5 2.9 2.5
3.0 3.4 3.0 V
2.0 2.4 2.0
0.42 0.55 0.55
0.13 0.55 0.55 V
±0.01 ±1 ±1 µA
0.01 1 1 µA
–2 –3 –5 µA
VCC = 4.5V; VI = 0.8V 35 35
Bus Hold current inputs
74ABTH16273
VCC = 4.5V; VI = 2.0V –75 –75
VCC = 5.5V; VI = 0 to 5.5V ±800
Power-off leakage
current
I
output current
O
Output High leakage
current
Additional supply current
per input pin
CC
74ABT16273
Additional supply current
per input pin
CC
74ABTH16273
1
pp
2
2
VCC= 0.0V; VO or VI 4.5V ±5.0 ±100 ±100 µA
VCC = 5.5V; VO = 2.5V –50 –70 –180 –50 –180 mA
VCC = 5.5V; VO = 5.5V; VI = GND or V
CC
VCC = 5.5V; Outputs High, VI = GND or V
VCC = 5.5V; Outputs Low, VI = GND or V
VCC = 5.5V; One input at 3.4V.
Other inputs at VCC or GND
VCC = 5.5V; One input at 3.4V.
Other inputs at VCC or GND
CC
CC
5.0 50 50 µA
0.2 1 1
8 19 19
5 100 100 µA
0.2 1 1 mA
74ABT16273
74ABTH16273
Temp = -40°C
to +85°C
UNIT
µA
AC CHARACTERISTICS
GND = 0V; tR = tF = 2.5ns; CL = 50pF; RL = 500Ω;
SYMBOL PARAMETER WAVEFORM
t
PLH
t
PHL
t
PHL
f
MAX
1998 Feb 27
LIMITS
T
V
amb
CC
= +25°C
= +5.0V
T
= –40 to +85 °C
amb
V
= +5.0V ±0.5V
CC
MIN TYP MAX MIN MAX
Propagation delay
nCP to nQx
Propagation delay
nMR
to nQx
1
2 1.9 3.7 4.3 1.9 5.3 ns
1.5
1.2
2.5
2.0
3.4
2.7
1.5
1.2
4.0
3.0
Maximum clock frequency 1 150 240 150 MHz
5
UNIT
ns
Page 6
Philips Semiconductors Product specification
16-bit D-type flip-flop
AC SETUP REQUIREMENTS
GND = 0V; tR = tF = 2.5ns; CL = 50pF; RL = 500Ω
LIMITS
T
= +25°C
SYMBOL PARAMETER WAVEFORM
tS(H)
tS(L)
th(H)
th(L)
tW(H)
tW(L)
Setup time, High or Low
nDx to nCP
Hold time, High or Low
nDx to nCP
Clock pulse width
High or Low
3
3
1
tW(L) Master Reset pulse width, Low 2 3.3 1.1 3.3 ns
t
REC
Recovery time
nMR + nCP
2 2.0 0.0 2.0 ns
AC WAVEFORMS
VM = 1.5V, VIN = GND to 2.7V
1/f
MAX
nQx
nCP
V
M
tW(H) tW(L)
t
PHL
V
M
V
M
t
PLH
V
M
V
M
0V
V
V
SH00056
OH
OL
Waveform 1. Propagation Delay, Clock Input to Output, Clock
Pulse Width, and Maximum Clock Frequency
nDx
nCP
amb
VCC = +5.0V
MIN TYP MIN
2.0
2.0
0
0
3.3
3.3
(H)
t
s
permitted to change for predictable output performance.
1.0
1.0
–0.6
–0.6
1.2
1.0
V
V
M
M
t
(H)
h
V
M
NOTE: The shaded areas indicate when the input is
Waveform 3. Data Setup and Hold Times
74ABTH16273
T
= –40 to +85 °C
amb
VCC = +5.0V ±0.5V
2.0
2.0
0
0
3.3
3.3
V
M
(L)
t
s
74ABT16273
UNIT
ns
ns
ns
V
M
0V
t
(L)
h
V
M
0V
SH00058
nMR
nCP
nQx
V
M
t
PHL
V
M
(L)
t
w
V
M
t
REC
V
M
0V
0V
V
OH
V
OL
SH00057
Waveform 2. Master Reset Pulse Width, Master Reset to Output
Delay and Master Reset to Clock Recovery Time
1998 Feb 27
6
Page 7
Philips Semiconductors Product specification
16-bit D-type flip-flop
TEST CIRCUIT AND WAVEFORM
V
CC
V
PULSE
GENERATOR
IN
D.U.T.
R
T
Test Circuit for Outputs
DEFINITIONS
RL = Load resistor; see AC CHARACTERISTICS for value.
C
= Load capacitance includes jig and probe capacitance;
L
see AC CHARACTERISTICS for value.
RT = Termination resistance should be equal to Z
pulse generators.
V
OUT
C
L
OUT
of
74ABT16273
74ABTH16273
t
90%
NEGATIVE
PULSE
R
L
POSITIVE
PULSE
10%
V
M
10% 10%
t
THL
t
TLH
90% 90%
V
M
W
V
M
(tF)
(tR)t
V
M
t
W
VM = 1.5V
Input Pulse Definition
INPUT PULSE REQUIREMENTS
FAMILY
74ABT16
Amplitude Rep. Rate t
W
3.0V 1MHz 500ns 2.5ns
90%
10%
t
R
t
TLH
THL
AMP (V)
0V
(tR)
(tF)
AMP (V)
0V
t
2.5ns
F
SH00059
1998 Feb 27
7
Page 8
Philips Semiconductors Product specification
16-bit D-type flip-flop
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1
74ABTH16273
74ABT16273
1998 Feb 27
8
Page 9
Philips Semiconductors Product specification
16-bit D-type flip-flop
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1mm SOT362-1
74ABTH16273
74ABT16273
1998 Feb 27
9
Page 10
Philips Semiconductors Product specification
74ABT16273
74ABTH16273
Data sheet status
Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
Definition
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1]
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
print code Date of release: 05-96
Document order number: 9397-750-03489
yyyy mmm dd
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