Datasheet 74ABT845N, 74ABT845DB, 74ABT845D, 74ABT845PW Datasheet (Philips)

Philips Semiconductors Product specification

8-bit bus interface latch with set and reset (3-State)

FEA TURES

•High speed parallel latches

•Ideal where high speed, light loading, or increased fan-in are

required with MOS microprocessors

•Broadside pinout

•Output capability: +64mA/–32mA

•Power-up 3-State

•Power-up reset

•Latch-up protection exceeds 500mA per Jedec Std 17

•ESD protection exceeds 2000 V per MIL STD 883 Method 3015

and 200 V per Machine Model

QUICK REFERENCE DAT A

SYMBOL PARAMETER

C

t

PLH

t

PHL

C

OUT

I

CCZ

IN

Propagation delay Dn to Qn

CL = 50pF; VCC = 5V 5.4 ns

Input capacitance VI = 0V or V

Output capacitance

Outputs disabled;

= 0V or V

V

O

Total supply current Outputs disabled; VCC = 5.5V 500 nA

74ABT845

DESCRIPTION

The 74ABT845 consists of eight D-type latches with 3-State outputs. In addition to the LE, OE additional OE OE

1, OE2) pins. The multiple Output enables allow multiuser control

pins, making a total of three Output Enable (OE0,

of the interface, e.g., CS

CONDITIONS = 25°C; GND = 0V

T

amb

CC

, MR and PRE pins, the 74ABT845 has two

, DMA, and RD/WR.

TYPICAL UNIT

4 pF

7 pF

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER

24-Pin Plastic DIP –40°C to +85°C 74ABT845 N 74ABT845 N SOT222-1 24-Pin plastic SO –40°C to +85°C 74ABT845 D 74ABT845 D SOT137-1 24-Pin Plastic SSOP Type II –40°C to +85°C 74ABT845 DB 74ABT845 DB SOT340-1 24-Pin Plastic TSSOP Type I –40°C to +85°C 74ABT845 PW 74ABT845PW DH SOT355-1

PIN CONFIGURA TION

1

OE0

2

OE1

3

D0

4

D1

5

D2

6

D3

7

D4

8

D5

9

D6 Q6

10 15

D7

11 14MR 12 13GND

24

V

CC

OE

23

2

Q0

22

Q1

21

Q2

20

Q3

19

Q4

18

Q5

17 16

Q7 PRE LE

PIN DESCRIPTION

PIN NUMBER SYMBOL FUNCTION

1, 2, 23 OE0 – OE2

3, 4, 5, 6,

7, 8, 9, 10

22, 21, 20, 19,18,

17, 16, 15

D0-D7 Data inputs

Q0-Q7 Data outputs 11 MR Master reset input (active-Low) 13 LE 14 PRE Preset input (active-Low)

12 GND Ground (0V) 24 V

CC

Output enable inputs (active-Low)

Latch enable input (active-High)

Positive supply voltage

TOP VIEW

SA00258

1995 Sep 06 853-1703 15702

1

Philips Semiconductors Product specification

8-bit bus interface latch with set and reset (3-State)

LOGIC SYMBOL (IEEE/IEC)

&

1

2 23 14 11 13

3 4 5 6 7 8 9

10

EN

S2 R C1

21D

22 21

20 19

18 17 16 15

SA00260

LOGIC SYMBOL

13

LE

14

PRE

11

MR

1

OE0

2 OE1

23 OE2

74ABT845

345678910

D0 D1 D2 D3 D4 D5 D6 D7

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

22 21 20 19 18 17 16 15

SA00259

FUNCTION TABLE

OUTPU

TS

OEnPR

E

INPUTS

MR LE Dn Qn

L L X X X H Preset L H L X X L Clear LLHHHHH

LLHHH

H

HLH

↓ ↓

l

h

L

H

L

H

H X X X X Z High impedance

L H H L X NC Hold

OPERATING

MODE

Transparent

Latched

LOGIC DIAGRAM

PRE

MR

D0

14

11

3

D

LQ

D1

4

PPPPPPPP

D

C C C C C C C C

LQ

D2

5

D

LQ

H = High voltage level h = High voltage level one set-up time prior to the High-to-Low LE

transition L = Low voltage level l = Low voltage level one set-up time prior to the High-to-Low LE

transition NC= No change X = Don’t care Z = High impedance “off” state ↓ = High-to-Low transition

D3

6

D

LQ

D4

7

D

LQ

D5

8

D

LQ

D6

9

D

LQ

D7

10

D

LQ

1995 Sep 06

OE0 OE OE2

13

LE

1 2

1

23

Q0

22

Q1

21

Q2

20

Q3

19

Q4

18

Q5

17

16

Q6

15

Q7

SA00261

2

Philips Semiconductors Product specification

8-bit bus interface latch with set and reset (3-State)

ABSOLUTE MAXIMUM RATINGS

SYMBOL

V

I

V

I V

I

OK

OUT

T

DC supply voltage –0.5 to +7.0 V

CC

DC input diode current VI < 0 –18 mA

IK

DC input voltage

I

DC output diode current VO < 0 –50 mA DC output voltage DC output current output in Low state 128 mA Storage temperature range –65 to 150 °C

stg

NOTES:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability .

2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.

3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

PARAMETER CONDITIONS RATING UNIT

3

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER LIMITS UNIT

V

V V V I

OH

I

OL

∆t/∆v Input transition rise or fall rate 0 5 ns/V

T

amb

DC supply voltage 4.5 5.5 V

CC

Input voltage 0 V

I

High-level input voltage 2.0 V

IH

Low-level input voltage 0.8 V

IL

High-level output current –32 mA Low-level output current 64 mA

Operating free-air temperature range –40 +85 °C

1,2

–1.2 to +7.0 V

output in Off or High state –0.5 to +5.5 V

Min Max

74ABT845

CC

V

1995 Sep 06

3

Philips Semiconductors Product specification

8-bit bus interface latch with set and reset (3-State)

DC ELECTRICAL CHARACTERISTICS

LIMITS

SYMBOL PARAMETER TEST CONDITIONS T

V

RST

I

OFF

I

PU/PD

I

OZH

I

OZL

I

CEX

I

CCH

I

CCL

I

CCZ

∆I

Input clamp voltage VCC = 4.5V; IIK = –18mA –0.9 –1.2 –1.2 V

IK

VCC = 4.5V; IOH = –3mA; VI = VIL or V

High–level output voltage VCC = 5.0V; IOH = –3mA; VI = VIL or V

OH

VCC = 4.5V; IOH = –32mA; VI = VIL or V

Low–level output voltage VCC = 4.5V; IOL = 64mA; VI = VIL or V

OL

Power-up output low

3

voltage

I

Input leakage current VCC = 5.5V; VI = GND or 5.5V ±0.01 ±1.0 ±1.0 µA

I

Power-off leakage current VCC = 0.0V; VO or V Power-up/down

3-state output current

4

VCC = 5.5V; IO = 1mA; VI = GND or V

4.5V ±5.0 ±100 ±100 µA

≤

I

VCC = 2.1V; VO = 0.5V; VOE = V VI = GND or V

CC

3-State output High current VCC = 5.5V; VO = 2.7V; VI = VIL or V 3-State output Low current VCC = 5.5V; VO = 0.5V; VI = VIL or V Output High leakage current VCC = 5.5V; VO = 5.5V; VI = GND or V

I

O

Output current

1

VCC = 5.5V; VO = 2.5V –50 –80 –180 –50 –180 mA VCC = 5.5V; Outputs High, VI = GND or V

Quiescent supply current VCC = 5.5V; Outputs Low, VI = GND or V

CC;

IH

CC

IH

CC

VCC = 5.5V; Outputs 3-State;

= GND or V

V

Additional supply current per

CC

input pin

2

I

VCC = 5.5V; one input at 3.4V, other inputs at V

CC

or GND

CC

NOTES:

1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

2. This is the increase in supply current for each input at 3.4V.

3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.

4. This parameter is valid for any V transition time of up to 100µsec is permitted.

between 0V and 2.1V with a transition time of up to 10msec. For VCC = 2.1V to VCC = 5V  10%, a

CC

= +25°C

amb

Min Typ Max Min Max

2.5 2.9 2.5 V

3.0 3.4 3.0 V

2.0 2.4 2.0 V

0.42 0.55 0.55 V

0.13 0.55 0.55 V

±5.0 ±50 ±50 µA

5.0 50 50 µ A

–5.0 –50 –50 µA

5.0 50 50 µ A

0.5 250 250 µA 24 30 30 mA

0.5 250 250 µA

0.5 1.5 1.5 mA

74ABT845

T

= –40°C

amb

to +85°C

UNIT

1995 Sep 06

4

Philips Semiconductors Product specification

8-bit bus interface latch with set and reset (3-State)

AC CHARACTERISTICS

GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω

SYMBOL PARAMETER WAVEFORM

t t

t

PLH PHL

PZH PZL

PHZ PLZ

Propagation delay Dn to Qn

Propagation delay LE to Qn

Propagation delay

to Qn

PRE Propagation delay

to Qn

MR Output enable time

n to Qn

OE Output disable time

n to Qn

OE

1

2

1

1 4

5 4

5

74ABT845

LIMITS

T

= -40 to

T

= +25oC

amb

= +5.0V

V

CC

Min Typ Max Min Max

1.0

2.2

2.0

2.8

2.2

3.0

2.4

3.1

1.0

2.0

1.9

2.2

3.9

5.4

5.1

6.4

4.9

5.3

4.9

5.9

3.8

4.7

4.6

4.7

5.4

6.8

6.6

7.9

6.6

6.8

6.4

7.3

5.4

6.1

6.2

6.4

amb

+85

= +5.0V ±0.5V

V

CC

1.0

2.2

2.0

2.8

2.2

3.0

2.4

3.1

1.0

2.0

1.9

2.2

o

C

6.2

7.8

7.5

8.9

7.8

7.4

7.3

8.5

6.3

6.7

7.2

7.0

UNIT

ns

AC SETUP REQUIREMENTS

GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω

LIMITS

T

= +25oC

SYMBOL PARAMETER WAVEFORM

amb

V

CC

= +5.0V

Min Typ Min

ts(H)

(L)

t

s

th(H)

(L)

t

h

Setup time, High or Low Dn to LE

Hold time, High or Low Dn to LE

3

2.8

3.5

1.0

1.4

–1.2 –0.6

tw(H) LE pulse width, High 3 3.0 1.5 3.0 ns

tw(L) PRE pulse width, Low 6 3.5 2.0 3.5 ns tw(L) MR pulse width, Low 6 2.8 1.3 2.8 ns

t

rec

t

rec

PRE recovery time 6 3.0 1.4 3.0 ns MR recovery time 6 3.4 1.6 3.4 ns

T

= -40 to +85oC

amb

= +5.0V ±0.5V

V

CC

2.8

3.5

1.0

UNIT

ns

1995 Sep 06

5

Philips Semiconductors Product specification

8-bit bus interface latch with set and reset (3-State)

AC WAVEFORMS

NOTE: For all waveforms, VM = 1.5V.

PRE

V

M

MR, Dn

t

PLH

Qn

V

M

Waveform 1. Propagation Delay, Data to Output,

Preset to Output, and Master Reset to Output

V

Dn

ts(H) th(H) ts(L) th(L)

LE

NOTE: The shaded areas indicate when the input is permitted

V

M

V

M

to change for predictable output performance.

Waveform 3. Data Setup and Hold Times and Latch Enable

Pulse Width

V

M

t

PHL

V

M

SA00254

V

M

tw(H)

V

M

V

M

SA00256

74ABT845

Dn

LE

Qn

Waveform 2. Propagation Delay, Latch Enable

OE

Qn

Waveform 4. 3-State Output Enable Time to High Level and

V

M

t

PLH

V

M

V

M

t

PHL

V

M

to Output

V

M

t

PZH

V

M

t

PHZ

V

M

Output Disable Time from High Level

SA00255

VOH–0.3V

0V

SA00066

OE

Qn

V

M

t

PZL

V

M

t

PLZ

V

M

VOL +0.3V V

OL

Waveform 5. 3-State Output Enable Time to Low Level and

Output Disable Time from Low Level

1995 Sep 06

SA00109

PRE, MR

Qn

V

M

LE

V

M

t

(L)

w

V

M

Waveform 6. Master Reset and Preset Pulse Width and Master

Reset and Preset to Latch Enable Recovery Time

6

t

REC

SA00257

Philips Semiconductors Product specification

8-bit bus interface latch with set and reset (3-State)

TEST CIRCUIT AND WAVEFORM

V

CC

R

OUT

L

R

L

of

PULSE

GENERATOR

V

IN

R

D.U.T.

T

V

OUT

C

L

Test Circuit for 3-State Outputs

SWITCH POSITION

TEST SWITCH

t t

PLZ PZL

closed closed

All other open

DEFINITIONS

RL = Load resistor; see AC CHARACTERISTICS for value.

= Load capacitance includes jig and probe capacitance;

C

L

see AC CHARACTERISTICS for value.

= Termination resistance should be equal to Z

R

T

pulse generators.

74ABT845

t

90%

7.0V NEGATIVE

PULSE

POSITIVE PULSE

10%

V

M

10% 10%

t

THL

t

TLH

90% 90%

V

M

Input Pulse Definition

INPUT PULSE REQUIREMENTS

FAMILY

Amplitude Rep. Rate t

74ABT 3.0V 1MHz 500ns 2.5ns 2.5ns

W

(tF)

(tR)t

t

W

90%

V

M

V

M

10%

VM = 1.5V

t

W

AMP (V)

0V

t

(tR)

TLH

(tF)

THL

AMP (V)

0V

t

R

F

SA00012

1995 Sep 06

7