Datasheet 74ABT843PW, 74ABT843N, 74ABT843DB, 74ABT843D Datasheet (Philips)

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Page 1

INTEGRATED CIRCUITS

74ABT843

9-bit interface latch with set and reset (3-State)

Product specification Supersedes data of 1995 Sep 06

IC23 Data Handbook

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1998 Jan 16

Page 2

Philips Semiconductors Product specification

9-bit bus interface latch with set and reset (3-State)

FEA TURES

•High speed parallel latches

•Extra data width for wide address/data paths or buses carrying

parity

•Ideal where high speed, light loading, or increased fan-in are

required with MOS microprocessors

•Slim DIP 300 mil package

•Broadside pinout

•Output capability: +64mA/–32mA

•Latch-up protection exceeds 500mA per Jedec Std 17

•ESD protection exceeds 2000V per MIL STD 883 Method 3015

and 200V per Machine Model

•Power-up 3-State

•Power-up reset

QUICK REFERENCE DATA

SYMBOL PARAMETER

PLH

PHL

OUT

CCZ

Propagation delay Dn to Qn

CL = 50pF; VCC = 5V 5.0 ns

Input capacitance VI = 0V or V

Output capacitance

Outputs disabled; VO = 0V or V

Total supply current Outputs disabled; VCC = 5.5V 500 nA

74ABT843

DESCRIPTION

The 74ABT843 Bus interface latch is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity.

The 74ABT843 consists of nine D-type latches with 3-State outputs. In addition to the LE and OE and Preset (PRE

) pin. These pins are ideal for parity bus interfacing in high performance systems. When MR if OE

is Low. When MR is High, data can be entered into the latch.

When PRE

is Low, the outputs are High, if OE is Low. PRE

overrides MR.

CONDITIONS

= 25°C; GND = 0V

amb

pins, it has a Master Reset (MR) pin

is Low, the outputs are Low

TYPICAL UNIT

4 pF

7 pF

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER

24-Pin Plastic DIP –40°C to +85°C 74ABT843 N 74ABT843 N SOT222-1 24-Pin plastic SO –40°C to +85°C 74ABT843 D 74ABT843 D SOT137-1 24-Pin Plastic SSOP Type II –40°C to +85°C 74ABT843 DB 74ABT843 DB SOT340-1 24-Pin Plastic TSSOP Type I –40°C to +85°C 74ABT843 PW 74ABT843PW DH SOT355-1

PIN CONFIGURATION

OE D0 D1 D2 D3 D4

D7 Q7

10 15

11 14MR 12 13GND

1 2 3 4 5 6 7 8 9

TOP VIEW

Q8 PRE LE

SA00250

PIN DESCRIPTION

PIN NUMBER SYMBOL FUNCTION

1 OE

2, 3, 4, 5, 6,

7, 8, 9, 10

23, 22, 21, 20,

19,18, 17, 16, 15

D0-D8 Data inputs

Q0-Q8 Data outputs 11 MR Master reset input (active-Low) 13 LE 14 PRE Preset input (active-Low)

12 GND Ground (0V) 24 V

Output enable input (active-Low)

Latch enable input (active rising edge)

Positive supply voltage

1998 Jan 16 853-1620 18864

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Philips Semiconductors Product specification

9-bit bus interface latch with set and reset (3-State)

LOGIC SYMBOL

2345678910

D0 D1 D2 D3 D4 D5 D6 D7 D8

PRE

OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8

23 22 21 20 19 18 17 16 15

SA00251

LOGIC SYMBOL (IEEE/IEC)

223

322 421 520 619 718 817 916

10 15

74ABT843

SA00252

FUNCTION TABLE

INPUTS OUTPUTS OPERATING MODE

OE PRE MR LE Dn Qn

L L X X X H Preset L H L X X L Clear L

L L

H X X X X Z High impedance

L H H L X NC Hold

H = High voltage level h = High voltage level one set-up time prior to the High-to-Low LE transition L = Low voltage level l = Low voltage level one set-up time prior to the High-to-Low LE transition NC= No change X = Don’t care Z = High impedance “off” state ↓ = High-to-Low transition

H H

↓ ↓

Transparent

Latched

1998 Jan 16

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Philips Semiconductors Product specification

9-bit bus interface latch with set and reset (3-State)

LOGIC DIAGRAM

PRE

PPPPPPPPP

C C C C C C C C

74ABT843

SA00253

ABSOLUTE MAXIMUM RA TINGS

SYMBOL

OUT

stg

DC supply voltage –0.5 to +7.0 V DC input diode current VI < 0 –18 mA DC input voltage DC output diode current VO < 0 –50 mA DC output voltage DC output current output in Low state 128 mA Storage temperature range –65 to 150 °C

PARAMETER CONDITIONS RATING UNIT

1, 2

–1.2 to +7.0 V

output in Off or High state –0.5 to +5.5 V

NOTES:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability .

2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.

3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

1998 Jan 16

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Philips Semiconductors Product specification

9-bit bus interface latch with set and reset (3-State)

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER LIMITS UNIT

Min Max

V V V I

∆t/∆v Input transition rise or fall rate 0 10 ns/V

amb

DC ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER TEST CONDITIONS T

RST

OFF

PU/IPD

OZH

OZL

CEX

CCH

CCL

CCZ

∆I

NOTES:

1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

2. This is the increase in supply current for each input at 3.4V.

3. For valid test results, data must not be loaded into the flip–flops (or latches) after applying the power.

4. This parameter is valid for any V transition time of up to 100µsec is permitted.

DC supply voltage 4.5 5.5 V Input voltage 0 V

High-level input voltage 2.0 V

Low-level input voltage 0.8 V

High-level output current –32 mA Low-level output current 64 mA

Operating free-air temperature range –40 +85 °C

LIMITS

= +25°C

amb

Min Typ Max Min Max

Input clamp voltage VCC = 4.5V; IIK = –18mA –0.9 –1.2 –1.2 V

VCC = 4.5V; IOH = –3mA; VI = VIL or V

High–level output voltage VCC = 5.0V; IOH = –3mA; VI = VIL or V

VCC = 4.5V; IOH = –32mA; VI = VIL or V Low–level output voltage VCC = 4.5V; IOL = 64mA; VI = VIL or V Power–up output low

voltage Input leakage current VCC = 5.5V; VI = GND or 5.5V ±0.01 ±1.0 ±1.0 µA

Power-off leakage current VCC = 0.0V; VO or V Power-up/down 3–state

output current

VCC = 5.5V; IO = 1mA; VI = V

≤ 4.5V ±5.0 ±100 ±100 µA

VCC = 2.0V; VO = 0.5V; V

GND or V

= V

3-State output High current VCC = 5.5V; VO = 2.7V; VI = VIL or V 3-State output Low current VCC = 5.5V; VO = 0.5V; VI = VIL or V Output high leakage current VCC = 5.5V; VO = 5.5V; VI = GND or V Output current

VCC = 5.5V; VO = 2.5V –50 –80 –180 –50 –180 mA

or GND 0.13 0.55 0.55 V

; VI =

VCC = 5.5V; Outputs High, VI = GND or V Quiescent supply current VCC = 5.5V; Outputs Low, VI = GND or V

VCC = 5.5V; Outputs 3-State;

Additional supply current per input pin

between 0V and 2.1V with a transition time of up to 10msec. For VCC = 2.1V to VCC = 5V  10%, a

VI = GND or V

VCC = 5.5V; one input at 3.4V,

other inputs at VCC or GND

2.5 2.9 2.5 V

3.0 3.4 3.0 V

2.0 2.4 2.0 V

0.42 0.55 0.55 V

±5.0 ±50 ±50 µA

5.0 50 50 µA

–5.0 –50 –50 µA

5.0 50 50 µA

0.5 250 250 µA 25 34 34 mA

0.5 250 250 µA

0.5 1.5 1.5 mA

74ABT843

= –40°C

amb

to +85°C

UNIT

1998 Jan 16

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Philips Semiconductors Product specification

9-bit bus interface latch with set and reset (3-State)

AC CHARACTERISTICS

SYMBOL PARAMETER WAVEFORM

PLH

PHL

PLH

PHL

PLH

PHL

PLH

PHL

PZH

PZL

PHZ

PLZ

Propagation delay Dn to Qn

Propagation delay LE to Qn

Propagation delay PRE

to Qn

Propagation delay MR to Qn

Output enable time OE to Qn

Output disable time OE to Qn

1 4

5 4

74ABT843

LIMITS

= -40 to

= +25oC

amb

VCC = +5.0V

Min Typ Max Min Max

1.6

2.2

2.0

2.8

2.2

3.0

2.5

3.1

1.0

2.0

2.9

2.2

3.6

5.0

4.1

4.8

4.7

5.2

5.0

5.5

2.7

4.2

4.9

5.0

5.2

6.3

5.6

6.3

6.2

6.5

6.3

6.8

4.2

5.5

6.2

6.3

amb

+85oC

= +5.0V ±0.5V

1.6

2.2

2.0

2.8

2.2

3.0

2.5

3.1

1.0

2.0

2.9

2.2

6.0

7.2

6.5

6.9

7.4

7.2

7.1

8.0

5.2

6.5

6.8

6.7

UNIT

AC SETUP REQUIREMENTS

GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω

LIMITS

= +25oC

SYMBOL PARAMETER WAVEFORM

amb

VCC = +5.0V

Min Typ Min

ts(H) ts(L)

th(H) th(L)

Setup time, High or Low Dn to LE

Hold time, High or Low Dn to LE

2.5

3.0

1.0

1.1

1.3

–1.0

–1.0 tw(H) LE pulse width, High 3 3.3 1.8 3.3 ns tw(L) PRE pulse width, Low 6 4.5 3.0 4.5 ns tw(L) MR pulse width, Low 6 5.5 4.0 5.5 ns t

rec

PRE recovery time 6 2.9 1.6 2.9 ns MR recovery time 6 3.6 2.0 3.6 ns

= -40 to +85oC

amb

VCC = +5.0V ±0.5V

2.5

3.0

1.0

UNIT

1998 Jan 16

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Philips Semiconductors Product specification

9-bit bus interface latch with set and reset (3-State)

AC WAVEFORMS

VM = 1.5V, VIN = GND to 3.0V

PRE

MR, Dn

PLH

Waveform 1. Propagation Delay, Data to Output,

Master Reset to Output, Preset to Output

(H) th(H) ts(L) th(L)

NOTE: The shaded areas indicate when the input is permitted

to change for predictable output performance.

Waveform 3. Data Setup and Hold Times and Latch Enable

Pulse Width

PHL

SA00254

tw(H)

SA00256

74ABT843

Waveform 2. Propagation Delay, Latch Enable

Waveform 4. 3-State Output Enable Time to High Level and

PLH

PHL

to Output

PZH

PHZ

Output Disable Time from High Level

SA00166

SA00255

–0.3V

PZL

PLZ

VOL +0.3V V

SA00109

Waveform 5. 3-State Output Enable Time to Low Level and

Output Disable Time from Low Level

TEST CIRCUIT AND WAVEFORM

PRE, MR

(L)

REC

SA00257

Waveform 6. Master Reset and Preset Pulse Width,

Master Reset and Preset to Latch Enable Recovery Time

1998 Jan 16

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Philips Semiconductors Product specification

9-bit bus interface latch with set and reset (3-State)

From Output Under Test

= 50 pF

DEFINITIONS

= Load capacitance includes jig and probe capacitance;

see AC CHARACTERISTICS for value.

500 Ω

Load Circuit

TEST S1

PLZ/tPZL

PHZ/tPZH

open

7 V

open

7 V

Open

GND

SA00012

74ABT843

1998 Jan 16

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Philips Semiconductors Product specification

9-bit bus interface latch with set and reset (3-State)

DIP24: plastic dual in-line package; 24 leads (300 mil) SOT222-1

74ABT843

1998 Jan 16

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Philips Semiconductors Product specification

9-bit bus interface latch with set and reset (3-State)

SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1

74ABT843

1998 Jan 16

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Philips Semiconductors Product specification

9-bit bus interface latch with set and reset (3-State)

SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm SOT340-1

74ABT843

1998 Jan 16

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Philips Semiconductors Product specification

9-bit bus interface latch with set and reset (3-State)

TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1

74ABT843

1998 Jan 16

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Philips Semiconductors Product specification

9-bit bus interface latch with set and reset (3-State)

NOTES

74ABT843

1998 Jan 16

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Philips Semiconductors Product specification

9-bit bus interface latch with set and reset (3-State)

Data sheet status

Objective specification

Preliminary specification

Product specification

Product status

Development

Qualification

Production

Definition

This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.

[1]

74ABT843

[1] Please consult the most recently issued datasheet before initiating or completing a design.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.

Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381

 Copyright Philips Electronics North America Corporation 1998

print code Date of release: 05-96 Document order number: 9397-750-03475

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