Datasheet 74ABT841PW, 74ABT841N, 74ABT841DB, 74ABT841D Datasheet (Philips)

Philips Semiconductors Product specification

74ABT84110-bit bus interface latch (3-State)

FEA TURES

•High speed parallel latches

•Extra data width for wide address/data paths or buses carrying

parity

•Ideal where high speed, light loading, or increased fan-in are

required with MOS microprocessors

•Slim DIP 300 mil package

•Broadside pinout

•Output capability: +64mA/–32mA

•Latch-up protection exceeds 500mA per Jedec Std 17

•ESD protection exceeds 2000 V per MIL STD 883 Method 3015

and 200 V per Machine Model

•Power-up 3-State

•Power-up reset

QUICK REFERENCE DAT A

SYMBOL PARAMETER

C

t

PLH

t

PHL

C

OUT

I

CCZ

IN

Propagation delay Dn to Qn

Input capacitance VI = 0V or V

Output capacitance

Total supply current Outputs disabled; VCC = 5.5V 500 nA

DESCRIPTION

The 74ABT841 Bus interface register is designed to provide extra data width for wider data/address paths of buses carrying parity.

The 74ABT841 consists of ten D-type latches with 3-State outputs. The flip-flops appear transparent to the data when Latch Enable (LE) is High. This allows asynchronous operation, as the output transition follows the data in transition. On the LE High-to-Low transition, the data that meets the setup and hold time is latched.

Data appears on the bus when the Output Enable (OE When OE

T

is High the output is in the High-impedance state.

CONDITIONS = 25°C; GND = 0V

amb

TYPICAL UNIT

CL = 50pF; VCC = 5V 4.1 ns

CC

Outputs disabled;

= 0V or V

V

O

CC

4 pF

7 pF

) is Low.

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER

24-Pin Plastic DIP –40°C to +85°C 74ABT841 N 74ABT841 N SOT222-1 24-Pin plastic SO –40°C to +85°C 74ABT841 D 74ABT841 D SOT137-1 24-Pin Plastic SSOP Type II –40°C to +85°C 74ABT841 DB 74ABT841 DB SOT340-1 24-Pin Plastic TSSOP Type I –40°C to +85°C 74ABT841 PW 74ABT841PW DH SOT355-1

PIN CONFIGURA TION

1

OE

2

D0

3

D1

4

D2

5

D3

6

D4

7

D5

8

D6

9

D7 Q7

10 15

D8

11 14D9 12 13GND

TOP VIEW

24

V

CC

Q0

23

Q1

22

Q2

21

Q3

20

Q4

19

Q5

18

Q6

17 16

Q8 Q9 LE

SA00247

PIN DESCRIPTION

PIN NUMBER SYMBOL FUNCTION

1 OE

2, 3, 4, 5, 6,

7, 8, 9, 10, 11

23, 22, 21, 20, 19,

18, 17, 16, 15, 14

D0-D9 Data inputs

Q0-Q9 Data outputs

13 LE 12 GND Ground (0V)

24 V

Output enable input (active-Low)

Latch enable input (active falling edge)

Positive supply voltage

CC

1995 Sep 06 853-1628 15703

1

Philips Semiconductors Product specification

10-bit bus interface latch (3-State)

LOGIC SYMBOL

234567891011

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9

13 LE

1OE

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9

23 22 21 20 19 18 17 16 15 14

SA00244

74ABT841

FUNCTION TABLE

INPUTS OUTPUTS

OE LE Dn Q0 – Q9

L L

H H

↓ ↓

L

H

l

h

L

H

L

H

H X X Z High impedance

L L X NC Hold

H = High voltage level h = High voltage level one set-up time prior to the High-to-Low LE

transition L = Low voltage level l = Low voltage level one set-up time prior to the High-to-Low LE

transition ↓ = High-to-Low LE transition NC= No change X = Don’t care Z = High impedance “off” state

OPERATING

MODE

Transparent

Latched

LOGIC SYMBOL (IEEE/IEC)

1

13

10 15 11 14

EN C1

223

1D

322 421 520 619 718 817 916

SA00245

1995 Sep 06

2

Philips Semiconductors Product specification

10-bit bus interface latch (3-State)

LOGIC DIAGRAM

D3

D

LQ

21

Q2

OE

D0

2

13

LE

1

D

LQ

D1

3

D

LQ

23

Q0

D2

4

22

Q1

5

D

LQ

Q3

20

D4

6

D

LQ

Q4

19

D5

7

D

LQ

Q5

74ABT841

Q7

16

D8

10

D

LQ

Q8

15

D9

11

D

LQ

14

Q9

SA00246

D

LQ

D7

9

D

LQ

17

Q6

D6

8

18

ABSOLUTE MAXIMUM RA TINGS

SYMBOL

V

CC

I

IK

V

I

OK

V

OUT

I

OUT

T

stg

DC supply voltage –0.5 to +7.0 V DC input diode current VI < 0 –18 mA DC input voltage DC output diode current VO < 0 –50 mA DC output voltage DC output current output in Low state 128 mA Storage temperature range –65 to 150 °C

PARAMETER CONDITIONS RATING UNIT

3

1, 2

–1.2 to +7.0 V

output in Off or High state –0.5 to +5.5 V

NOTES:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability .

2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.

3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER LIMITS UNIT

Min Max

V

CC

V V V I

OH

I

OL

∆t/∆v Input transition rise or fall rate 0 5 ns/V

T

amb

DC supply voltage 4.5 5.5 V Input voltage 0 V

I

High-level input voltage 2.0 V

IH

Low-level input voltage 0.8 V

IL

High-level output current –32 mA Low-level output current 64 mA

Operating free-air temperature range –40 +85 °C

CC

V

1995 Sep 06

3

Philips Semiconductors Product specification

Additional supply current per

One input at 3.4V, other inputs at V

or

∆I

CC

i

2

GND; V

5V

0.5

1.5

mA

10-bit bus interface latch (3-State)

DC ELECTRICAL CHARACTERISTICS

LIMITS

SYMBOL PARAMETER TEST CONDITIONS T

Min Typ Max Min Max

V

RST

Input clamp voltage VCC = 4.5V; IIK = –18mA –0.9 –1.2 –1.2 V

IK

VCC = 4.5V; IOH = –3mA; VI = VIL or V

High-level output voltage VCC = 5.0V; IOH = –3mA; VI = VIL or V

OH

VCC = 4.5V; IOH = –32mA; VI = VIL or V

Low-level output voltage VCC = 4.5V; IOL = 64mA; VI = VIL or V

OL

Power-up output low

3

voltage

I

Input leakage Control pins VCC = 5.5V; VI = GND or 5.5V ±0.01 ±1.0 ±1.0 µA

I

VCC = 5.5V; IO = 1mA; VI = GND or V

IH IH

IH

CC

current Data pins VCC = 5.5V; VI = GND or 5.5V ±5 ±100 ±100 µA

I

OFF

I

PU/PD

IIH + I

IIL + I

I

CEX

I

CCH

I

CCL

I

CCZ

∆I

I

Power-off leakage current VCC = 0.0V; VO or VI ≤ 4.5V ±5.0 ±100 ±100 µA Power-up/down 3–state

output current 3-State output High current VCC = 5.5V; VO = 2.7V; VI = VIL or V

OZH

3-State output Low current VCC = 5.5V; VO = 0.5V; VI = VIL or V

OZL

4

Output high leakage current VCC = 5.5V; VO = 5.5V; VI = GND or V

O

Output current

1

Quiescent supply current VCC = 5.5V; Outputs Low, VI = GND or V

VCC = 2.0V; VO = 0.5V; VI = GND or VCC;

= V

V

OE

CC

IH IH

CC

VCC = 5.5V; VO = 2.5V –50 –100 –180 –50 –180 mA VCC = 5.5V; Outputs High, VI = GND or V

CC

VCC = 5.5V; Outputs 3–State;

= GND or V

V

CC

nput pin

I

2

CC

= 5.

CC

NOTES:

1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

2. This is the increase in supply current for each input at 3.4V.

3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.

4. This parameter is valid for any V transition time of up to 100µsec is permitted.

between 0V and 2.1V with a transition time of up to 10msec. For VCC = 2.1V to VCC = 5V  10%, a

CC

= +25°C

amb

2.5 3.5 2.5 V

3.0 4.0 3.0 V

2.0 2.6 2.0 V

0.42 0.55 0.55 V

0.13 0.55 0.55 V

±5.0 ±50 ±50 µA

5.0 50 50 µA

–5.0 –50 –50 µA

5.0 50 50 µA

0.5 250 250 µA 25 38 38 mA

0.5 250 250 µA

0.5 1.5 1.5 mA

74ABT841

T

= –40°C

amb

to +85°C

UNIT

AC CHARACTERISTICS

GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω

SYMBOL PARAMETER WAVEFORM

t

PLH

t

PHL

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

1995 Sep 06

Propagation delay Dn to Qn

Propagation delay LE to Qn

Output enable time to High and Low level

Output disable time from High and Low level

LIMITS

T

= -40 to

T

amb

V

= +25oC = +5.0V

CC

amb

+85

= +5.0V ±0.5V

V

CC

o

C

UNIT

Min Typ Max Min Max

2

1 4

5 4

5

2.1

2.0

2.1

2.8

1.0

2.2

2.7

2.8

4.1

4.0

4.1

4.6

3.0

4.1

4.7

4.6

5.5

5.9

6.2

4.5

5.6

6.2

6.1

2.1

2.0

2.1

2.8

1.0

2.2

2.7

2.8

6.2

6.5

6.7

5.3

6.3

7.1

6.5

ns

4

Philips Semiconductors Product specification

10-bit bus interface latch (3-State)

AC SETUP REQUIREMENTS

GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω

SYMBOL PARAMETER WAVEFORM

ts(H)

(L)

t

s

th(H)

(L)

t

h

tw(H)

(L)

t

w

AC WAVEFORMS

VM = 1.5V, VIN = GND to 3.0V

Setup time, High or Low Dn to LE

Hold time, High or Low Dn to LE

LE pulse width High or Low

LE

Qn

V

M

t

PHL

tw(H)

V

M

V

M

V

M

t

PLH

V

M

74ABT841

LIMITS

T

= +25oC

amb

= +5.0V

V

CC

Min Typ Min

3

2.5

1.5

1.0

0.0

0.2

–0.8

1 3.3 1.9 3.3 ns

OE

Qn

T

= -40 to +85oC

amb

= +5.0V ±0.5V

V

CC

2.5

1.5

1.0

V

M

t

PZH

V

M

t

PHZ

V

M

UNIT

ns

VOH–0.3V

0V

SA00248SA00248

Waveform 1. Propagation Delay, Latch Enable Input to Output,

and Enable Pulse Width

Dn

Qn

V

M

t

PLH

V

M

t

PHL

V

M

V

M

SA00064

Waveform 2. Propagation Delay for Data to Outputs

V

Dn

t

(H) th(H) ts(L) th(L)

s

LE

V

M

V

M

V

M

V

M

SA00066

Waveform 4. 3-State Output Enable Time to High Level and

Output Disable Time from High Level

OE

Qn

V

M

t

PZL

V

M

t

PLZ

V

M

VOL+0.3V

0V

SA00067

Waveform 5. 3-State Output Enable Time to Low Level and

Output Disable Time from Low Level

NOTE: The shaded areas indicate when the input is permitted to change

for predictable output performance.

Waveform 3. Data Setup and Hold Times

1995 Sep 06

SA00249

5

Philips Semiconductors Product specification

10-bit bus interface latch (3-State)

TEST CIRCUIT AND WAVEFORM

V

CC

V

PULSE

GENERATOR

IN

R

D.U.T.

T

Test Circuit for 3-State Outputs

SWITCH POSITION

TEST SWITCH

t t

PLZ PZL

closed closed

All other open

DEFINITIONS

RL = Load resistor; see AC CHARACTERISTICS for value.

= Load capacitance includes jig and probe capacitance;

C

L

see AC CHARACTERISTICS for value.

= Termination resistance should be equal to Z

R

T

pulse generators.

V

OUT

C

L

OUT

74ABT841

t

90%

7.0V NEGATIVE

R

L

R

L

PULSE

POSITIVE PULSE

10%

V

M

10% 10%

t

THL

t

TLH

90% 90%

V

M

W

V

M

(tF)

(tR)t

V

M

t

W

VM = 1.5V

Input Pulse Definition

INPUT PULSE REQUIREMENTS

FAMILY

of

Amplitude Rep. Rate t

74ABT 3.0V 1MHz 500ns 2.5ns 2.5ns

W

90%

10%

t

R

t

TLH

THL

AMP (V)

0V

(tR)

(tF)

AMP (V)

0V

t

F

SA00012

1995 Sep 06

6