Datasheet 74ABT823PW, 74ABT823N, 74ABT823DB, 74ABT823D Datasheet (Philips)

Philips Semiconductors Product specification

9-bit D-type flip-flop with reset and enable
(3-State)

FEA TURES

•High speed parallel registers with positive edge-triggered D-type

flip-flops

•Ideal where high speed, light loading, or increased fan-in are

required with MOS microprocessors

•Output capability: +64mA/–32mA

•Latch-up protection exceeds 500mA per Jedec Std 17

•ESD protection exceeds 2000 V per MIL STD 883 Method 3015

and 200 V per Machine Model

•Power-up 3-State

•Power-up Reset

QUICK REFERENCE DAT A

SYMBOL PARAMETER

C

t

PLH

t

PHL

C

OUT

I

CCZ

IN

Propagation delay
CP to Qn

CL = 50pF; VCC = 5V 4.4 ns

Input capacitance VI = 0V or V

Output capacitance

Outputs disabled;

= 0V or V

V

O

Total supply current Outputs disabled; VCC =5.5V 500 nA

74ABT823

DESCRIPTION

The 74ABT823 Bus interface Register is designed to eliminate the
extra packages required to buffer existing registers and provide
extra data width for wider data/address paths of buses carrying
parity.

The 74ABT823 is a 9-bit wide buffered register with Clock Enable
(CE

) and Master Reset (MR) which are ideal for parity bus

interfacing in high microprogrammed systems.
The register is fully edge-triggered. The state of each D input, one

set-up time before the Low-to-High clock transition is transferred to
the corresponding flip-flop’s Q output.

CONDITIONS
= 25°C; GND = 0V

T

amb

CC

CC

TYPICAL UNIT

4 pF

7 pF

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER

24-Pin Plastic DIP –40°C to +85°C 74ABT823 N 74ABT823 N SOT222-1
24-Pin plastic SO –40°C to +85°C 74ABT823 D 74ABT823 D SOT137-1
24-Pin Plastic SSOP Type II –40°C to +85°C 74ABT823 DB 74ABT823 DB SOT340-1
24-Pin Plastic TSSOP Type I –40°C to +85°C 74ABT823 PW 74ABT823PW DH SOT355-1

PIN CONFIGURA TION

1

OE

2

D0

3

D1

4

D2

5

D3

6

D4

7

D5

8

D6

9

D7 Q7

10 15

D8

11 14MR
12 13GND

TOP VIEW

24

V

CC

Q0

23

Q1

22

Q2

21

Q3

20

Q4

19

Q5

18

Q6

17
16

Q8
CE
CP

PIN DESCRIPTION

PIN NUMBER SYMBOL FUNCTION

1 OE

2, 3, 4, 5, 6,

7, 8, 9, 10

23, 22, 21, 20,

19,18, 17, 16, 15

D0-D8 Data inputs

Q0-Q8 Data outputs

13 CP

14 CE

11 MR
12 GND Ground (0V)

24 V

CC

Output enable input
(active-Low)

Clock pulse input (active
rising edge)

Clock enable input
(active-Low)

Master reset input
(active-Low)

Positive supply voltage

SA00227

1995 Sep 06 853–1617 15703

1

Philips Semiconductors Product specification

9-bit D-type flip-flop with reset and enable
(3-State)

LOGIC SYMBOL

2345678910

D0 D1 D2 D3 D4 D5 D6 D7 D8

13

CP

14

CE

11

MR

1

OE

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8

23 22 21 20 19 18 17 16 15

SA00228

LOGIC SYMBOL (IEEE/IEC)

1
11
14
13

10 15

EN
R
G1

1C2

223

2D

322
421
520
619
718
817
916

74ABT823

SA00229

FUNCTION TABLE

INPUTS OUTPUTS OPERATING MODE

OE MR CE CP Dn Q0 – Q8

L L X X X L Clear
L H L ↑ h H Load and read data
L H L ↑ l L
L H H ↑ X NC Hold

H X X X X Z High impedance

H = High voltage level
h = High voltage level one set-up time prior to the Low-to-High

clock transition
L = Low voltage level
l = Low voltage level one set-up time prior to the Low-to-High

NC = No change
X = Don’t care
Z = High impedance “off” state

↑ = Low to High clock transition
↑

clock transition

LOGIC DIAGRAM

14

CE

CP

D0

13

D

RQ

D1

2

CP CP CP CP CP CP CP CP CP

3

D

RQ

D2

4

D

RQ

D3

5

D

RR Q

= Not a Low-to-High clock transition

D4

D

RQ

6

D5

D

RQ

7

D6

8

D

RQ

D7

9

D

RQ

D8

10

D

RQ

1995 Sep 06

MR

OE

11

1

23

Q0

Q1

22

Q2

21

Q3

20

Q4

19

Q5

18

Q6

17

Q7

16

15

Q8

SA00230

2

Philips Semiconductors Product specification

9-bit D-type flip-flop with reset and enable
(3-State)

ABSOLUTE MAXIMUM RATINGS

SYMBOL

V

I

V

I
V

I

OK

OUT

OUT

T

CC

IK

stg

DC supply voltage –0.5 to +7.0 V
DC input diode current VI < 0 –18 mA
DC input voltage

I

DC output diode current VO < 0 –50 mA
DC output voltage
DC output current output in Low state 128 mA
Storage temperature range –65 to 150 °C

NOTES:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the

device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .

2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction

temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.

3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

PARAMETER CONDITIONS RATING UNIT

3

3

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER LIMITS UNIT

V

CC

V
V
V
I

OH

I

OL

∆t/∆v Input transition rise or fall rate 0 5 ns/V

T

amb

DC supply voltage 4.5 5.5 V
Input voltage 0 V

I

High-level input voltage 2.0 V

IH

Low-level input voltage 0.8 V

IL

High-level output current –32 mA
Low-level output current 64 mA

Operating free-air temperature range –40 +85 °C

1, 2

–1.2 to +7.0 V

output in Off or High state –0.5 to +5.5 V

Min Max

74ABT823

CC

V

1995 Sep 06

3

Philips Semiconductors Product specification

9-bit D-type flip-flop with reset and enable
(3-State)

DC ELECTRICAL CHARACTERISTICS

LIMITS

SYMBOL PARAMETER TEST CONDITIONS T

Min Typ Max Min Max

V

V

V

V

RST

I

OFF

IPU/I

I

OZH

I

OZL

I

CEX

I

CCH

I

CCL

I

CCZ

∆I

I

Input clamp voltage VCC = 4.5V; IIK = –18mA –0.9 –1.2 –1.2 V

IK

VCC = 4.5V; IOH = –3mA; VI = VIL or V

High-level output voltage VCC = 5.0V; IOH = –3mA; VI = VIL or V

OH

VCC = 4.5V; IOH = –32mA; VI = VIL or V

Low-level output voltage VCC = 4.5V; IOL = 64mA; VI = VIL or V

OL

Power-up output low

3

voltage

I

Input leakage current VCC = 5.5V; VI = GND or 5.5V ±0.01 ±1.0 ±1.0 µA

I

VCC = 5.5V; IO = 1mA; VI = GND or V

IH

IH

IH

IH

CC

Power-off leakage current VCC = 0.0V; VO or VI ≤ 4.5V ±5.0 ±100 ±100 µA
Power-up/down 3-State

PD

output current

4

3-State output High current VCC = 5.5V; VO = 2.7V; VI = VIL or V
3-State output Low current VCC = 5.5V; VO = 0.5V; VI = VIL or V
Output High leakage current VCC = 5.5V; VO = 5.5V; VI = GND or V

O

Output current

1

Quiescent supply current VCC = 5.5V; Outputs Low, VI = GND or V

VCC = 2.0V; VO = 0.5V; VOE = VCC;

= GND or V

V

I

CC

IH

IH

CC

VCC = 5.5V; VO = 2.5V –50 –100 –180 –50 –180 mA
VCC = 5.5V; Outputs High, VI = GND or V

CC

CC

VCC = 5.5V; Outputs 3-State;

= GND or V

V

Additional supply current per

CC

input pin

2

I

VCC = 5.5V; one input at 3.4V,
other inputs at V

CC

or GND

CC

NOTES:

1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

2. This is the increase in supply current for each input at 3.4V.

3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.

4. This parameter is valid for any V
transition time of up to 100µsec is permitted.

between 0V and 2.1V with a transition time of up to 10msec. For VCC = 2.1V to VCC = 5V  10%, a

CC

= +25°C

amb

2.5 2.9 2.5 V

3.0 3.4 3.0 V

2.0 2.4 2.0 V

0.42 0.55 0.55 V

0.13 0.55 0.55 V

±5.0 ±50 ±50 µA

5.0 50 50 µA

–5.0 –50 –50 µA

5.0 50 50 µA

0.5 250 250 µA
27 34 34 mA

0.5 250 250 µA

0.5 1.5 1.5 mA

74ABT823

T

= –40°C

amb

to +85°C

UNIT

AC CHARACTERISTICS

GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω

SYMBOL PARAMETER WAVEFORM

f

MAX

t

PLH

t

PHL

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

1995 Sep 06

Maximum clock frequency 1 125 200 125 MHz
Propagation delay

CP to Qn
Propagation delay

to Qn

MR
Output enable time

to High and Low level
Output disable time

from High and Low level

1

2 2.0 4.1 6.3 2.0 7.1 ns
4

5
4

5

LIMITS

T

T

amb

V

= +25oC
= +5.0V

CC

amb

= +5.0V ±0.5V

V

CC

Min Typ Max Min Max

2.1

2.2

1.0

2.2

2.7

2.8

4.3

4.4

3.0

4.1

4.8

5.0

5.9

6.1

4.5

5.6

6.2

6.4

2.1

2.2

1.0

2.2

2.7

2.8

4

= -40 to

o

C

+85

6.8

6.7

5.3

6.3

6.9

6.9

UNIT

ns

ns

ns

Philips Semiconductors Product specification

9-bit D-type flip-flop with reset and enable
(3-State)

AC SETUP REQUIREMENTS

GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω

LIMITS

T

= +25oC

SYMBOL PARAMETER WAVEFORM

ts(H)

(L)

t

s

th(H)

(L)

t

h

tw(H)

(L)

t

w

ts(H)

(L)

t

s

th(H)

(L)

t

h

tw(L) MR pulse width, Low 2 5.5 4.0 5.5 ns

t

rec

Setup time, High or Low
Dn to CP

Hold time, High or Low
Dn to CP

CP pulse width
High or Low

Setup time, High or Low

to CP

CE
Hold time, High or Low

to CP

CE

Recovery time

to CP

MR

3

3

1

3

3

2 2.5 0.6 2.5 ns

amb

= +5.0V

V

CC

Min Typ Min

2.1

2.1

1.3

1.3

2.9

3.8

2.0

3.3

1.0

2.0

0.5

0.2

0.0

–0.3

1.9

2.8

–0.5

1.5

–1.4

0.7

T

= -40 to +85oC

amb

= +5.0V ±0.5V

V

CC

2.1

2.1

1.3

1.3

2.9

3.8

2.0

3.3

1.0

2.0

74ABT823

UNIT

ns

ns

ns

ns

ns

1995 Sep 06

5

Philips Semiconductors Product specification

9-bit D-type flip-flop with reset and enable
(3-State)

AC WAVEFORMS

VM = 1.5V, VIN = GND to 3.0V

1/f

MAX

CP

Q

n

V

M

tW(H) tW(L)

t

PHL

V

M

Waveform 1. Propagation Delay, Clock Input to Output, Clock

Pulse Width, and Maximum Clock Frequency

Dn, CE

CP

V

V

M

M

(H) th(H) ts(L) th(L)

t

s

V

M

t

PLH

V

M

V

MVM

V

M

SA00159

V

M

74ABT823

MR

CP

Qn

V

M

t

PHL

Waveform 2. Master Reset Pulse WIdth, Master Reset to Output

Delay and Master Reset to Clock Recovery Time

OE

Qn

V

M

t

PZH

V

M

(L)

t

w

V

M

V

M

t

PHZ

V

M

t

REC

V

M

SA00232

VOH–0.3V

0V

NOTE: The shaded areas indicate when the input is permitted to change for
predictable output performance.

SA00231

Waveform 3. Data Setup and Hold Times

OE

Qn

V

M

t

PZL

V

M

t

PLZ

V

M

VOL+0.3V

0V

SA00067

Waveform 5. 3-State Output Enable Time to Low Level and

Output Disable Time from Low Level

SA00066

Waveform 4. 3-State Output Enable Time to High Level and

Output Disable Time from High Level

1995 Sep 06

6

Philips Semiconductors Product specification

9-bit D-type flip-flop with reset and enable
(3-State)

TEST CIRCUIT AND WAVEFORM

V

CC

R

OUT

L

R

L

of

PULSE

GENERATOR

V

IN

R

D.U.T.

T

V

OUT

C

L

Test Circuit for 3-State Outputs

SWITCH POSITION

TEST SWITCH

t

PLZ

t

PZL

closed
closed

All other open

DEFINITIONS

RL = Load resistor; see AC CHARACTERISTICS for value.

= Load capacitance includes jig and probe capacitance;

C

L

see AC CHARACTERISTICS for value.

= Termination resistance should be equal to Z

R

T

pulse generators.

74ABT823

t

90%

7.0V
NEGATIVE

PULSE

POSITIVE
PULSE

10%

V

M

10% 10%

t

THL

t

TLH

90% 90%

V

M

Input Pulse Definition

INPUT PULSE REQUIREMENTS

FAMILY

Amplitude Rep. Rate t

74ABT 3.0V 1MHz 500ns 2.5ns 2.5ns

W

(tF)

(tR)t

t

W

90%

V

M

V

M

10%

VM = 1.5V

t

W

AMP (V)

0V

t

(tR)

TLH

(tF)

THL

AMP (V)

0V

t

R

F

SA00012

1995 Sep 06

7