Datasheet 74ABT821PW, 74ABT821N, 74ABT821DB, 74ABT821D Datasheet (Philips)

Philips Semiconductors Product specification

10-bit D-type flip-flop; positive-edge trigger
(3-State)

FEA TURES

•High speed parallel registers with positive edge-triggered D-type

flip-flops

•Ideal where high speed, light loading, or increased fan-in are

required with MOS microprocessors

•Output capability: +64mA/–32mA

•Latch-up protection exceeds 500mA per Jedec Std 17

•ESD protection exceeds 2000 V per MIL STD 883 Method 3015

and 200 V per Machine Model

•Power-up 3-State

•Power-up Reset

DESCRIPTION

The 74ABT821 high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.

The 74ABT821 Bus interface Register is designed to eliminate the
extra packages required to buffer existing registers and provide

QUICK REFERENCE DAT A

SYMBOL PARAMETER

C

t

PLH

t

PHL

C

OUT

I

CCZ

IN

Propagation delay
CP to Qn

Input capacitance VI = 0V or V
Output capacitance Outputs disabled; VO = 0V or V
Total supply current Outputs disabled; VCC =5.5V 500 nA

CL = 50pF; VCC = 5V 4.6 ns

extra data width for wider data/address paths of buses carrying
parity.

The 74ABT821 is a buffered 10-bit wide version of the
74ABT374/74ABT534 functions.

The 74ABT821 is a 10-bit, edge triggered register coupled to ten
3-State output buffers. The two sections of the device are controlled
independently by the clock (CP) and Output Enable (OE
gates.

The register is fully edge triggered. The state of each D input, one
set-up time before the Low-to-High clock transition is transferred to
the corresponding flip-flop’s Q output.

The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors.

The active Low Output Enable (OE
independent of the register operation. When OE
the register appears at the outputs. When OE
are in high impedance ”off” state, which means they will neither drive
nor load the bus.

T

CONDITIONS
= 25°C; GND = 0V

amb

CC

CC

74ABT821

) control

) controls all ten 3-State buffers

is Low, the data in

is High, the outputs

TYPICAL UNIT

4 pF
7 pF

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER

24-Pin Plastic DIP –40°C to +85°C 74ABT821 N 74ABT821 N SOT222-1
24-Pin plastic SO –40°C to +85°C 74ABT821 D 74ABT821 D SOT137-1
24-Pin Plastic SSOP Type II –40°C to +85°C 74ABT821 DB 74ABT821 DB SOT340-1
24-Pin Plastic TSSOP Type I –40°C to +85°C 74ABT821 PW 74ABT821PW DH SOT355-1

PIN CONFIGURA TION

1

OE

2

D0

3

D1

4

D2

5

D3

6

D4

7

D5

8

D6

9

D7 Q7

10 15

D8

11 14D9
12 13GND

TOP VIEW

24

V

CC

Q0

23

Q1

22

Q2

21

Q3

20

Q4

19

Q5

18

Q6

17
16

Q8
Q9
CP

SA00223

PIN DESCRIPTION

PIN NUMBER SYMBOL FUNCTION

1 OE

2, 3, 4, 5, 6,

7, 8, 9, 10, 11

23, 22, 21, 20, 19,

18, 17, 16, 15, 14

D0-D9 Data inputs

Q0-Q9 Data outputs

13 CP
10 GND Ground (0V)

20 V

CC

Output enable input
(active-Low)

Clock pulse input (active
rising edge)

Positive supply voltage

1995 Sep 06 853-1616 15703

1

Philips Semiconductors Product specification

10-bit D-type flip-flop; positive-edge trigger
(3-State)

LOGIC SYMBOL

234567891011

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9

13

1CPOE

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9

23 22 21 20 19 18 17 16 15 14

SA00224

LOGIC SYMBOL (IEEE/IEC)

1

13

223
322
421
520
619
718
817

916
10 15
11 14

EN

C2

2D

74ABT821

1

SA00225

FUNCTION TABLE

INPUTS INTERNAL OUTPUTS OPERATING MODE

OE CP Dn REGISTER Q0 – Q9

L
L

↑
↑

l

h

L

H

L

H

L ↑ X NC NC Hold

H
H

↑
↑

Dn

X

NC

Dn

Z
Z

H = High voltage level
h = High voltage level one set-up time

prior to the Low-to-High clock transition
L = Low voltage level
l = Low voltage level one set-up time

prior to the Low-to-High clock transition

LOGIC DIAGRAM

D0

2

D

CP Q

D1

3

D

CP Q

D2

4

D

CP Q

D3

5

D

CP Q

Load and read register

Disable outputs

NC= No change
X = Don’t care
Z = High impedance “off” state
↑ = Low to High clock transition

= Not a Low-to-High clock transition

↑

D4

6

D

CP Q

D5

7

D

CP Q

D6

8

D

CP Q

D7

9

D

CP Q

D8

10

D

CP Q

D9

11

D

CP Q

13

CP

1

OE

1995 Sep 06

Q0

23

Q1

22

Q2

21

Q3

20

Q4

19

Q5

18

Q6

17

Q7

16

Q8

15

14

Q9

SA00226

2

Philips Semiconductors Product specification

10-bit D-type flip-flop; positive-edge trigger
(3-State)

ABSOLUTE MAXIMUM RATINGS

SYMBOL

V

I

V

I

V

I

OK

OUT

OUT

T

CC

IK

stg

DC supply voltage –0.5 to +7.0 V
DC input diode current VI < 0 –18 mA
DC input voltage

I

DC output diode current VO < 0 –50 mA
DC output voltage
DC output current output in Low state 128 mA
Storage temperature range –65 to 150 °C

NOTES:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the

device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .

2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction

temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.

3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

PARAMETER CONDITIONS RATING UNIT

3

3

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER LIMITS UNIT

V

CC

V
V
V
I

OH

I

OL

∆t/∆v Input transition rise or fall rate 0 10 ns/V

T

amb

DC supply voltage 4.5 5.5 V
Input voltage 0 V

I

High-level input voltage 2.0 V

IH

Low-level input voltage 0.8 V

IL

High-level output current –32 mA
Low-level output current 64 mA

Operating free-air temperature range –40 +85 °C

1, 2

–1.2 to +7.0 V

output in Off or High state –0.5 to +5.5 V

Min Max

74ABT821

CC

V

1995 Sep 06

3

Philips Semiconductors Product specification

10-bit D-type flip-flop; positive-edge trigger
(3-State)

DC ELECTRICAL CHARACTERISTICS

LIMITS

SYMBOL PARAMETER TEST CONDITIONS T

V

V

V

V

RST

I

OFF

IPU/I

I

OZH

I

OZL

I

CEX

I

CCH

I

CCL

I

CCZ

∆I

Input clamp voltage VCC = 4.5V; IIK = –18mA –0.9 –1.2 –1.2 V

IK

VCC = 4.5V; IOH = –3mA; VI = VIL or V

High-level output voltage VCC = 5.0V; IOH = –3mA; VI = VIL or V

OH

VCC = 4.5V; IOH = –32mA; VI = VIL or V

Low-level output voltage VCC = 4.5V; IOL = 64mA; VI = VIL or V

OL

Power-up output low

3

voltage

I

Input leakage current VCC = 5.5V; VI = GND or 5.5V ±0.01 ±1.0 ±1.0 µA

I

Power-off leakage current VCC = 0.0V; VO or V
Power-up/down 3-State

PD

output current

4

VCC = 5.5V; IO = 1mA; VI = GND or V

4.5V ±5.0 ±100 ±100 µA

≤

I

VCC = 2.0V; VO = 0.5V; VI = GND or VCC;

= V

V

OE

CC

3-State output High current VCC = 5.5V; VO = 2.7V; VI = VIL or V
3-State output Low current VCC = 5.5V; VO = 0.5V; VI = VIL or V
Output High leakage current VCC = 5.5V; VO = 5.5V; VI = GND or V

I

O

Output current

1

VCC = 5.5V; VO = 2.5V –50 –100 –180 –50 –180 mA
VCC = 5.5V; Outputs High, VI = GND or V

Quiescent supply current VCC = 5.5V; Outputs Low, VI = GND or V

IH

IH

IH

IH

CC

IH

IH

CC

CC

CC

VCC = 5.5V; Outputs 3-State;

= GND or V

V

Additional supply current per

CC

input pin

2

I

VCC = 5.5V; one input at 3.4V,
other inputs at V

CC

or GND

CC

NOTES:

1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

2. This is the increase in supply current for each input at 3.4V.

3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.

4. This parameter is valid for any V
transition time of up to 100µsec is permitted.

between 0V and 2.1V with a transition time of up to 10msec. For VCC = 2.1V to VCC = 5V  10%, a

CC

= +25°C

amb

Min Typ Max Min Max

2.5 2.9 2.5 V

3.0 3.4 3.0 V

2.0 2.4 2.0 V

0.42 0.55 0.55 V

0.13 0.55 0.55 V

±5.0 ±50 ±50 µA

5.0 50 50 µA

–5.0 –50 –50 µA

5.0 50 50 µA

0.5 250 250 µA
25 38 38 mA

0.5 250 250 µA

0.5 1.5 1.5 mA

74ABT821

T

= –40°C

amb

to +85°C

UNIT

AC CHARACTERISTICS

GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω

SYMBOL PARAMETER WAVEFORM

f

MAX

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

1995 Sep 06

Maximum clock frequency 1 125 185 125 ns
Propagation delay

CP to Qn
Output enable time

to High and Low level
Output disable time

from High and Low level

1

3
4

3
4

LIMITS

T

T

amb

V

= +25oC
= +5.0V

CC

amb

= +5.0V ±0.5V

V

CC

Min Typ Max Typ Max

2.1

2.8

1.0

2.2

2.7

2.8

4.1

4.6

3.0

4.1

4.7

4.6

5.6

6.2

4.5

5.6

6.2

6.1

2.1

2.8

1.0

2.2

2.7

2.8

4

= -40 to

o

+85

C

6.2

6.7

5.3

6.3

6.7

6.5

UNIT

ns

ns

ns

Philips Semiconductors Product specification

ÉÉÉ

ÉÉÉ

10-bit D-type flip-flop; positive-edge trigger
(3-State)

AC SETUP REQUIREMENTS

GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω

SYMBOL PARAMETER WAVEFORM

ts(H)

(L)

t

s

th(H)

(L)

t

h

tw(H)

(L)

t

w

AC WAVEFORMS

VM = 1.5V, VIN = GND to 3.0V

Setup time, High or Low
Dn to CP

Hold time, High or Low
Dn to CP

CP pulse width
High or Low

1/f

MAX

2

2

1

LIMITS

T

amb

V

CC

= +25oC
= +5.0V

T

= -40 to +85oC

amb

= +5.0V ±0.5V

V

CC

Min Typ Min

2.1

2.1

1.3

1.3

2.9

3.8

Dn

0.5

0.3

0.0

–0.3

1.8

2.8

2.1

2.1

1.3

1.3

2.9

3.8

V

V

M

M

74ABT821

UNIT

ns

ns

ns

V

V

M

M

CP

Q

n

V

M

tW(H) tW(L)

t

PHL

V

M

t

PLH

V

M

V

M

SA00159

Waveform 1. Propagation Delay, Clock Input to Output, Clock

Pulse Width, and Maximum Clock Frequency

OE

Qn

V

M

t

PZH

V

M

t

PHZ

V

M

VOH–0.3V

0V

SA00066

Waveform 3. 3–State Output Enable Time to High Level and

Output Disable Time from High Level

ts(H) th(H) ts(L) th(L)

CP

NOTE: The shaded areas indicate when the input is permitted
to change for predictable output performance.

V

M

V

M

SA00107

Waveform 2. Data Setup and Hold Times

OE

Qn

V

M

t

PZL

V

M

t

PLZ

V

M

VOL+0.3V

0V

SA00067

Waveform 4. 3–State Output Enable Time to Low Level and

Output Disable Time from Low Level

1995 Sep 06

5

Philips Semiconductors Product specification

10-bit D-type flip-flop; positive-edge trigger
(3-State)

TEST CIRCUIT AND WAVEFORM

V

CC

7.0V

R

OUT

L

R

L

of

PULSE

GENERATOR

V

IN

R

D.U.T.

T

V

OUT

C

L

Test Circuit for 3-State Outputs

SWITCH POSITION

TEST SWITCH

t
t

PLZ
PZL

closed
closed

All other open

DEFINITIONS

RL = Load resistor; see AC CHARACTERISTICS for value.

= Load capacitance includes jig and probe capacitance;

C

L

see AC CHARACTERISTICS for value.

= Termination resistance should be equal to Z

R

T

pulse generators.

74ABT821

t

90%

NEGATIVE
PULSE

POSITIVE
PULSE

10%

V

M

10% 10%

t

THL

t

TLH

90% 90%

V

M

W

V

M

(tF)

(tR)t

V

M

t

W

VM = 1.5V

Input Pulse Definition

INPUT PULSE REQUIREMENTS

FAMILY

Amplitude Rep. Rate t

W

74ABT 3.0V 1MHz 500ns 2.5ns 2.5ns

90%

10%

t

R

t

TLH

THL

AMP (V)

0V

(tR)

(tF)

AMP (V)

0V

t

F

SA00012

1995 Sep 06

6