Datasheet 74ABT74N, 74ABT74DB, 74ABT74D Datasheet (Philips)

Philips Semiconductors Product specification

CC

74ABT74Dual D-type flip-flop

QUICK REFERENCE DAT A

CONDITIONS

= 25°C;

SYMBOL PARAMETER

T

amb

GND = 0V

TYPICAL UNIT

Propagation

IN

CC

delay CPn to

n

Qn, Q Output to

Output skew Input

capacitance Total supply

current

CL = 50pF;

= 5V

V

CC

VI = 0V or V

CC

Outputs disabled;

= 5.5V

V

CC

3.0

2.5

0.5 ns

3 pF

50 µA

t

PLH

t

PHL

t

OSLH

t

OSHL

C

I

PIN CONFIGURA TION

R

CP0 S

GND

D1 D0

D1 Q0 Q

1 2 3 4 5 6

0

14

V

CC

13

D1

R

12

D1

11

CP1

10

SD1

9

Q1

87

Q1

PIN DESCRIPTION

PIN NUMBER SYMBOL NAME AND FUNCTION

1, 2, 3, 4, 10,

11, 12, 13

RDn, Dn,

CPn, S

Dn

Data inputs

5, 6, 8, 9 Qn, Qn Data outputs

7 GND Ground (0V)

14 V

Positive supply voltage

CC

LOGIC SYMBOL

212

ns

SF00045

DESCRIPTION

The 74ABT74 is a dual positive edge-triggered D-type flip-flop featuring individual data, clock, set, and reset inputs; also true and complementary outputs. Set (S

D) and reset (RD) are asynchronous active low inputs and operate independently of the clock input. When set and reset are inactive (high), data at the D input is transferred to the Q and Q

outputs on the low-to-high transition of the clock. Data must be stable just one setup time prior to the low-to-high transition of the clock for predictable operation. Clock triggering occurs at a voltage level and is not directly related to the transition time of the positive-going pulse. Following the hold time interval, data at the D input may be changed without affecting the levels of the output.

LOGIC SYMBOL (IEEE/IEC)

4 3 2 1

10

11 12 13

&

S

C1

1D

R

S

C2

2D R

5

6

9

8

SF00047

LOGIC DIAGRAM

4, 10

S

D

1, 13

D

R

5, 9

Q

VCC = Pin 14 GND = Pin 7

3 4 1

11 10 13

D0 D1

CP0 S

D0 RD0 CP1

D1

S

D1

R

Q0 Q0Q1Q1

56 98

SA00359

CP

D

VCC = Pin 14 GND = Pin 7

3, 11

2, 12

6, 8

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER

14-Pin Plastic DIP –40°C to +85°C 74ABT74 N 74ABT74 N SOT27-1 14-Pin plastic SO –40°C to +85°C 74ABT74 D 74ABT74 D SOT108-1 14-Pin Plastic SSOP Type II –40°C to +85°C 74ABT74 DB 74ABT74 DB SOT337-1 14-Pin Plastic TSSOP Type I –40°C to +85°C 74ABT74 PW 74ABT74PW DH SOT402-1

1

853-1813 157931995 Sep 22

Q

SF00048

Philips Semiconductors Product specification

OPERATING

SYMBOL

PARAMETER

UNIT

74ABT74Dual D-type flip-flop

FUNCTION TABLE

INPUTS OUTPUTS

SD RD CP D Q Q

OPERATING

MODE

L H X X H L Asynchronous set H L X X L H

Asynchronous

reset L L X X H H Undetermined* H H ↑ h H L Load “1” H H ↑ l L H Load “0” H H ↑ X NC NC Hold

NOTES:

H = High voltage level h = High voltage level one setup time prior to low-to-high

clock transition L = Low voltage level l = Low voltage level one setup time prior to low-to-high

clock transition NC= No change from the previous setup X = Don’t care ↑ = Low-to-high clock transition

= Not low-to-high clock transition

↑

* = This setup is unstable and will change when either set

or reset return to the high level.

ABSOLUTE MAXIMUM RATINGS

SYMBOL

V

CC

I

IK

V

I

OK

V

OUT

I

OUT

T

stg

DC supply voltage –0.5 to +7.0 V DC input diode current VI < 0 –18 mA DC input voltage DC output diode current VO < 0 –50 mA DC output voltage DC output current output in Low state 40 mA Storage temperature range –65 to 150 °C

PARAMETER CONDITIONS RATING UNIT

3

1, 2

–1.2 to +7.0 V

output in Off or High state –0.5 to +5.5 V

NOTES:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability .

2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.

3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

RECOMMENDED OPERATING CONDITIONS

LIMITS

MIN MAX

V

CC

V V V I

OH

I

OL

∆t/∆v Input transition rise or fall rate 0 10 ns/V

T

amb

DC supply voltage 4.5 5.5 V Input voltage 0 V

I

High-level input voltage 2.0 V

IH

Low-level input voltage 0.8 V

IL

High-level output current –15 mA Low-level output current 20 mA

Operating free-air temperature range –40 +85 °C

CC

V

1995 Sep 22

2

Philips Semiconductors Product specification

74ABT74Dual D-type flip-flop

DC ELECTRICAL CHARACTERISTICS

LIMITS

T

= –40°C

SYMBOL PARAMETER TEST CONDITIONS

T

amb

= +25°C

MIN TYP MAX MIN MAX

V

I

OFF

I

CEX

I

∆I

Input clamp voltage VCC = 4.5V; IIK = –18mA –0.9 –1.2 –1.2 V

IK

High-level output voltage VCC = 4.5V; IOH = –15mA; VI = VIL or V

OH

Low-level output voltage VCC = 4.5V; IOL = 20mA; VI = VIL or V

OL

I

Input leakage current VCC = 5.5V; VI = GND or 5.5V ±0.01 ±1.0 ±1.0 µA

I

IH

2.5 2.9 2.5 V

0.35 0.5 0.5 V

Power-off leakage current VCC = 0.0V; VO or VI ≤ 4.5V ±5.0 ±100 ±100 µA Output High leakage current VCC = 5.5V; VO = 5.5V; VI = GND or V

I

Output current

O

Quiescent supply current VCC = 5.5V; VI = GND or V

CC

Additional supply current per

CC

input pin

1

2

VCC = 5.5V; VO = 2.5V –50 –75 –180 –50 –180 mA

VCC = 5.5V; One data input at 3.4V, other inputs at V

or GND

CC

5.0 50 50 µA

2 50 50 µA

0.25 500 500 µA

NOTES:

1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

2. This is the increase in supply current for each input at 3.4V.

3. For valid test results, data must not be loaded into the flip-flop or latch after applying the power.

amb

to +85°C

UNIT

AC ELECTRICAL CHARACTERISTICS

GND = 0V; tR = tF = 2.5ns; CL = 50pF, RL = 500Ω

LIMITS

SYMBOL PARAMETER W AVEFORM

amb

V

CC

= +25°C

= +5.0V

T

= –40°C to +85°C

amb

= +5.0V ±0.5V

V

CC

UNIT

T

MIN TYP MAX MIN MAX

f

MAX

t

PLH

t

PHL

t

PLH

t

PHL

t

OSHL

t

OSLH

Maximum clock frequency 1 180 250 150 MHz Propagation delay

CPn to Qn, Q Propagation delay

n, Rn to Qn, Qn

S Output to Output skew

1

An or Bn to Y

n

1

3

n

4 0.5 0.6 0.6 ns

1.0

3.0

2.5

3.4

2.9

4.2

3.5

4.9

4.5

1.0

4.7

4.0

6.2

5.2

NOTE:

1. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the the same direction, either HIGH–to-LOW (t parameter guaranteed by design.

) or LOW-to-HIGH (t

OSHL

OSLH

AC SETUP REQUIREMENTS

GND = 0V; tR = tF = 2.5ns; CL = 50pF, RL = 500Ω

LIMITS

T

= +25°C

SYMBOL PARAMETER WAVEFORM

amb

V

CC

= +5.0V

MIN TYP MIN

t

(H)

su

(L)

t

su

t

(H)

h

(L)

t

h

t

(H)

w

(L)

t

w

t

(L) SDn, RDn pulse width, low 3 2.0 1.3 2.2 ns

w

t

rec

Setup time, high or low Dn to CPn

Hold time, high or low Dn to CPn

CPn pulse width, high or low

Recovery time

Dn, RDn to CPn

S

1

2.6

2.4 0

0

1.7

1.4

–1.4 –1.4

1.0

2 2.1 1.4 2.4 ns

T

= –40°C to +85°C

amb

= +5.0V ±0.5V

V

CC

2.6

2.4 0

0

2.1

UNIT

ns

);

1995 Sep 22

3

Philips Semiconductors Product specification

74ABT74Dual D-type flip-flop

AC WAVEFORMS

VM = 1.5V, VIN = GND to 3.0V The shaded areas indicate when the input is permitted to change for predictable output performance

Dn

CPn

V

tsu(L) th(L)

Qn

V

M

1/f

max

V

M

t

PLH

t

PHL

tw(H)

V

M

V

M

V

M

V

tsu(H) th(H)

t

(L)

w

M

Waveform 1. Propagation delay for data to output,

data setup time and hold times, and clock width,

and maximum clock frequency

SDn or RDn

CPn

V

M

t

rec

Waveform 2. Recovery time for set or reset to clock

t

PLH

t

PHL

tw(L)

V

M

(L)

t

PHL

t

w

V

PLH

V

M

V

M

V

M

V

M

V

M

SF00050

V

M

V

M

t

PHL

V

M

t

PLH

V

M

SF00049

SDn

V

M

RDn

Qn

Waveform 3. Propagation delay for set and reset to output,

set and reset pulse width

INPUT

V

M

SF00051

OUTPUT

OUTPUT N same part

t

PLH

MIN

t

PLH

MAX

t

PHL

MIN

t

PHL

MAX

t

OSLH

Waveform 4. Common edge skew

t

OSHL

SA00381

1995 Sep 22

4

Philips Semiconductors Product specification

74ABT74Dual D-type flip-flop

TEST CIRCUIT AND WAVEFORMS

V

CC

PULSE

GENERATOR

V

IN

R

D.U.T.

T

V

OUT

R

C

L

Test Circuit for Outputs

DEFINITIONS

RL = Load resistor; see AC CHARACTERISTICS for value.

= Load capacitance includes jig and probe capacitance;

C

L

see AC CHARACTERISTICS for value.

= T ermination resistance should be equal to Z

R

T

pulse generators.

OUT

of

NEGATIVE PULSE

POSITIVE PULSE

FAMILY

74ABT

t

90%

10%

V

M

10% 10%

t

THL

t

TLH

90% 90%

V

M

W

(tF)

(tR)t

t

W

VM = 1.5V

Input Pulse Definition

INPUT PULSE REQUIREMENTS

Amplitude Rep. Rate t

3.0V 1MHz 500ns 2.5ns

AMP (V)

90%

V

M

0V

t

(tR)

TLH

(tF)

THL

AMP (V)

V

M

10%

0V

t

W

t

R

F

2.5ns

SH00067

1995 Sep 22

5