Page 1
INTEGRATED CIRCUITS
74ABT657
Octal transceiver with parity
generator/checker (3-State)
Product specification 1995 Dec 11
IC23 Data Handbook
Page 2
Philips Semiconductors Product specification
Octal transceiver with parity generator/checker
(3-State)
FEA TURES
•Combinational functions in one package
•Low static and dynamic power dissipation with high speed and
high output drive
•Output capability: +64mA/–32mA
•Power-up 3-State
•Latch-up protection exceeds 500mA per Jedec Std 17
•ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
DESCRIPTION
The 74ABT657 high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
The 74ABT657 is an octal transceiver featuring non-inverting buffers
with 3-State outputs and an 8-bit parity generator/checker, and is
intended for bus-oriented applications. The buffers have a
guaranteed current sinking capability of 64mA. The
Transmit/Receive (T/R
flow through the bidirectional transceivers. Transmit (active-High)
enables data from A ports to B ports; Receive (active-Low) enables
data from B ports to A ports.
) input determines the direction of the data
The Output Enable (OE
placing them in a high impedance condition when the OE
High. The parity select (ODD/EVEN
of odd or even parity systems. The parity (PARITY) pin is an output
from the generator/checker when transmitting from the port A to B
= High) and an input when receiving from port B to A port (T/R
(T/R
= Low). When transmitting (T/R = High) the parity select
(ODD/EVEN
the number of High bits. The parity (PARITY) output then goes to the
logic state determined by the parity select (ODD/EVEN
by the number of High bits on port A. For example, if the parity
select (ODD/EVEN
High bits on port A is odd, then the parity (PARITY) output will be
High, transmitting even parity. If the number of High bits on port A is
even, then the parity (PARITY) output will be Low, keeping even
parity. When in receive mode (T/R
determine the number of High bits. If parity select (ODD/EVEN
Low (even parity) and the number of Highs on port B is:
(1) odd and the parity (PARITY) input is High, then ERROR
High, signifying no error.
(2) even and the parity (PARITY) input is High, then ERROR
asserted Low, indicating an error.
74ABT657
) input disables both the A and B ports by
input is
) input gives the user the option
) input is set, then the A port data is polled to determine
) setting and
) is set Low (even parity), and the number of
= Low) the B port is polled to
) is
will be
will be
QUICK REFERENCE DATA
SYMBOL PARAMETER
t
PLH
t
PHL
C
C
I
CCZ
IN
I/O
Propagation delay
An to Bn or Bn to An
Input capacitance VI = 0V or V
I/O capacitance
Total supply current Outputs disabled; VCC =5.5V 500 nA
CL = 50pF; VCC = 5V 3.3 ns
Outputs disabled;
= 0V or V
V
O
CONDITIONS
= 25°C; GND = 0V
T
amb
CC
CC
TYPICAL UNIT
4 pF
7 pF
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER
24-Pin Plastic DIP –40°C to +85°C 74ABT657 N 74ABT657 N SOT222-1
24-Pin plastic SO –40°C to +85°C 74ABT657 D 74ABT657 D SOT137-1
24-Pin Plastic SSOP Type II –40°C to +85°C 74ABT657 DB 74ABT657 DB SOT340-1
24-Pin Plastic TSSOP Type I –40°C to +85°C 74ABT657 PW 74ABT657PW DH SOT355-1
PIN CONFIGURATION
1OE
T/R
2
A0
3
A1
4
A2
5
A3
6
A4
7
V
CC
8
A5
9
A6
10
A7
ODD/EVEN
11
ERROR
TOP VIEW
24
23
22
21
20
19
18
17
16
15
14
1312
B0
B1
B2
B3
GND
GND
B4
B5
B6
B7
PARITY
SA00181
PIN DESCRIPTION
SYMBOL PIN NUMBER NAME AND FUNCTION
13 PARITY Parity output
11 ODD/EVEN Parity select input
12 ERROR Error output
1 T/R Transmit/receive input
2, 3, 4, 5,
6, 8, 9, 10
23, 22, 21, 20,
17, 16, 15, 14
24 OE Output enable input (active-Low)
18, 19 GND Ground (0V)
7 V
A0 - A7 A port 3-State outputs
B0 - B7 B port 3-State outputs
CC
Positive supply voltage
1995 Dec 1 1 853–1615 16106
2
Page 3
Philips Semiconductors Product specification
Octal transceiver with parity generator/checker
(3-State)
LOGIC SYMBOL
1
24
11
234568910
A0 A1 A2 A3 A4 A5 A6 A7
T/R
OE
ODD/EVEN
B0 B1 B2 B3
23 22 21 20 17 16 15 14
PARITY
ERROR
B4 B5 B6 B7
13
12
SA00182
LOGIC SYMBOL (IEEE/IEC)
74ABT657
1
24
11
223
322
421
520
617
816
915
10 14
0BUSBTOA
0
0
1BUSATOB
M
2
1
2HIGHZ
G3[EVEN]
G4[ODD]
2K =
0
1,3[EVEN]
1,4[ODD]
0,3[EVEN
0,4]ODD
2
13
12
SA00194
FUNCTION TABLE
NUMBER OF HIGH INPUTS
0, 2, 4, 6, 8
1, 3, 5, 7
Don’t care H X X Z Z 3-State
H = High voltage level
L = Low voltage level
X = Don’t care
Z = High impedance ”off” state
INPUTS
INPUT/
OUTPUT
OUTPUTS
OE T/R ODD/EVEN PARITY ERROR OUTPUTS MODE
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
L
L
L
H
H
L
L
L
L
H
L
H
H
L
L
H
L
H
H
L
L
H
L
H
L
H
L
L
H
H
L
H
L
Z
Z
H
L
L
H
Z
Z
L
H
H
L
Transmit
Transmit
Receive
Receive
Receive
Receive
Transmit
Transmit
Receive
Receive
Receive
Receive
1995 Dec 1 1
3
Page 4
Philips Semiconductors Product specification
Octal transceiver with parity generator/checker
(3-State)
LOGIC DIAGRAM
1
T/R
24
OE
2
A0
3
A1
4
A2
5
A3
6
A4
8
A5
9
A6
23
22
21
20
17
16
15
74ABT657
B0
B1
B2
B3
B4
B5
B6
ODD/EVEN
10
A7
11
14
B7
13
PARITY
12
ERROR
SA00215
1995 Dec 1 1
4
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Philips Semiconductors Product specification
SYMBOL
PARAMETER
UNIT
Octal transceiver with parity generator/checker
(3-State)
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
I
V
I
V
I
OK
OUT
OUT
T
CC
IK
stg
DC supply voltage –0.5 to +7.0 V
DC input diode current VI < 0 –18 mA
DC input voltage
I
DC output diode current VO < 0 –50 mA
DC output voltage
DC output current output in Low state 128 mA
Storage temperature range –65 to 150 °C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
PARAMETER CONDITIONS RATING UNIT
3
3
RECOMMENDED OPERATING CONDITIONS
V
CC
V
V
V
I
OH
I
OL
∆t/∆v Input transition rise or fall rate 0 5 ns/V
T
amb
DC supply voltage 4.5 5.5 V
Input voltage 0 V
I
High-level input voltage 2.0 V
IH
Low-level input voltage 0.8 V
IL
High-level output current –32 mA
Low-level output current 64 mA
Operating free-air temperature range –40 +85 °C
1, 2
–1.2 to +7.0 V
output in Off or High state –0.5 to +5.5 V
LIMITS
Min Max
74ABT657
CC
V
1995 Dec 1 1
5
Page 6
Philips Semiconductors Product specification
Octal transceiver with parity generator/checker
(3-State)
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL PARAMETER TEST CONDITIONS
V
V
V
Input clamp voltage VCC = 4.5V; IIK = –18mA –0.9 –1.2 –1.2 V
IK
VCC = 4.5V; IOH = –3mA; VI = VIL or V
High-level output voltage VCC = 5.0V; IOH = –3mA; VI = VIL or V
OH
VCC = 4.5V; IOH = –32mA; VI = VIL or V
Low-level output voltage VCC = 4.5V; IOL = 64mA; VI = VIL or V
OL
I
Input leakage Control pins VCC = 5.5V; VI = GND or 5.5V ±0.01 ±1.0 ±1.0 µA
I
IH
IH
IH
IH
current Data pins VCC = 5.5V; VI = GND or 5.5V ±5 ±100 ±100 µA
I
OFF
IPUI
IIH + I
IIL + I
I
CEX
I
CCH
I
CCL
I
CCZ
Power-off leakage current VCC 0.0V; VO or VI ≤ 4.5V ±5.0 ±100 ±100 µA
Power-up/down 3-State
PD
output current
3-State output High current VCC = 5.5V; VO = 2.7V; VI = VIL or V
OZH
3-State output Low current VCC = 5.5V; VO = 0.5V; VI = VIL or V
OZL
3
Output High leakage current VCC = 5.5V; VO = 5.5V; VI = GND or V
I
O
Output current
1
Quiescent supply current VCC = 5.5V; Outputs Low, VI = GND or V
VCC 2.0V; VO = 0.5V; VI = GND or VCC;
= V
V
OE
CC
IH
IH
CC
VCC = 5.5V; VO = 2.5V –50 –80 –180 –50 –180 mA
VCC = 5.5V; Outputs High, VI = GND or V
CC
CC
VCC = 5.5V; Outputs 3-State;
= GND or V
V
I
CC
Outputs enabled, one data input at 3.4V ,
other inputs at V
∆I
Additional supply current per
CC
input pin
2
Outputs 3-State, one data input at 3.4V , other
inputs at V
or GND; VCC = 5.5V
CC
or GND; VCC = 5.5V
CC
Outputs 3-State, one enable input at 3.4V ,
other inputs at V
or GND; VCC = 5.5V
CC
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. This parameter is valid for any V
transition time of up to 100µsec is permitted.
between 0V and 2.1V with a transition time of up to 10msec. For VCC = 2.1V to VCC = 5V 10%, a
CC
T
= +25°C
amb
Min Typ Max Min Max
2.5 3.5 2.5 V
3.0 4.0 3.0 V
2.0 2.6 2.0 V
0.42 0.55 0.55 V
±5.0 ±50 ±50 µA
5.0 50 50 µA
–5.0 –50 –50 µA
5.0 50 50 µA
0.5 250 250 µA
20 30 30 mA
0.5 250 250 µA
0.5 1.5 1.5 mA
50 250 250 µA
0.5 1.5 1.5 mA
74ABT657
T
= –40°C
amb
to +85°C
UNIT
1995 Dec 1 1
6
Page 7
Philips Semiconductors Product specification
Octal transceiver with parity generator/checker
(3-State)
AC CHARACTERISTICS
GND = 0V; tR = tF = 2.5ns; CL = 50pF, RL = 500Ω
LIMITS
T
= +25oC
SYMBOL PARAMETER WAVEFORMS
amb
V
CC
= +5.0V
Min Typ Max Min Max
t
t
t
t
t
t
t
t
t
t
t
t
t
t
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
Propagation delay
An to Bn or Bn to An
Propagation delay
An to PARITY
Propagation delay
ODD/EVEN
to PARITY, ERROR
Propagation delay
Bn to ERROR
Propagation delay
PARITY to ERROR
Output enable time
1
to High or Low level
Output disable time
from High or Low level
2
1, 2
1, 2
1, 2
1, 2
3, 4
3, 4
1.1
1.2
2.5
2.8
1.7
1.9
3.9
4.0
2.7
3.2
1.3
1.9
2.4
2.7
3.3
3.0
6.5
7.0
5.0
5.0
9.2
9.6
6.0
6.4
3.8
4.4
5.1
5.4
5.0
4.3
8.7
9.1
6.6
6.6
11.7
12.1
7.6
8.0
5.6
7.0
7.0
7.6
NOTES:
1. These delay times reflect the 3-State recovery time only and do not include the delay through the buffers and the parity check circuitry which
affect the ERROR
output. To assure
drivers (B to A), through the parity check circuitry (same as A to PARITY), and to the ERROR
valid
information at the ERROR pin, time must be allowed for the signal to propagate through the
output.
+ (A to PARITY).
T
amb
V
Valid
data at the ERROR pin ≥ (B to A)
74ABT657
= –40 to +85oC
= +5.0V ±10%
CC
1.1
1.2
2.5
2.8
1.7
1.9
3.9
4.0
2.7
3.2
1.3
1.9
2.4
2.7
5.5
4.8
10.1
10.6
7.3
7.3
13.8
14.5
9.4
9.4
6.6
8.2
7.6
8.1
UNIT
ns
ns
ns
ns
ns
ns
ns
AC WAVEFORMS
NOTE: For all waveforms, VM = 1.5V.
An, Bn
An, Bn
ODD/EVEN
ODD/EVEN
PARITY
PARITY
PARITY,
PARITY,
ERROR
ERROR
V
V
M
M
t
t
PHL
PHL
Waveform 1. Propagation Delay For Inverting Output
OE V
An, Bn
PARITY, ERROR
M
t
PZH
Waveform 3. 3-State Output Enable Time to High Level and
Output Disable Time from High Level
V
V
M
M
t
t
PLH
PLH
V
V
M
M
V
M
V
M
t
PHZ
V
V
M
M
SA00219
–0.3V
V
OH
SA00221
An, Bn
ODD/EVEN
PARITY
An, Bn,
PARITY,
ERROR
V
M
t
PLH
V
M
t
PHL
V
M
V
M
SA00220
Waveform 2. Propagation Delay For Non-Inverting Output
OE
An, Bn
PARITY, ERROR
0V
V
M
t
PZL
V
M
t
PLZ
V
M
V
+0.3V
OL
0V
SA00222
Waveform 4. 3-State Output Enable Time to Low Level and
Output Disable Time from Low Level
1995 Dec 1 1
7
Page 8
Philips Semiconductors Product specification
Octal transceiver with parity generator/checker
(3-State)
TEST CIRCUIT AND WAVEFORM
V
CC
7.0V
R
OUT
L
R
L
FAMILY
of
74ABT 3.0V 1MHz 500ns 2.5ns 2.5ns
PULSE
GENERATOR
V
IN
R
D.U.T.
T
V
OUT
C
L
Test Circuit for 3-State Outputs
SWITCH POSITION
TEST SWITCH
t
t
PLZ
PZL
closed
closed
All other open
DEFINITIONS
RL = Load resistor; see AC CHARACTERISTICS for value.
= Load capacitance includes jig and probe capacitance;
C
L
see AC CHARACTERISTICS for value.
= T ermination resistance should be equal to Z
R
T
pulse generators.
90%
NEGATIVE
PULSE
POSITIVE
PULSE
10%
t
W
V
M
10% 10%
(tF)
t
THL
(tR)t
t
TLH
90% 90%
V
M
t
W
VM = 1.5V
Input Pulse Definition
INPUT PULSE REQUIREMENTS
Amplitude Rep. Rate t
74ABT657
90%
V
M
t
TLH
THL
V
M
10%
t
W
R
AMP (V)
0V
(tR)
(tF)
AMP (V)
0V
t
F
SA00012
1995 Dec 1 1
8
Page 9
Philips Semiconductors Product specification
Octal transceiver with parity generator/checker
(3-State)
DIP24: plastic dual in-line package; 24 leads (300 mil) SOT222-1
SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm SOT340-1
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1
74ABT657
1995 Dec 1 1
9
Page 10
Philips Semiconductors Product specification
Octal transceiver with parity generator/checker
(3-State)
NOTES
74ABT657
1995 Dec 1 1
10
Page 11
Philips Semiconductors Product specification
Octal transceiver with parity generator/checker
(3-State)
74ABT657
DEFINITIONS
Data Sheet Identification Product Status Definition
Objective Specification
Preliminary Specification
Product Specification
Formative or in Design
Preproduction Product
Full Production
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing
or modification.
LIFE SUPPORT APPLICA TIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Philips Semiconductors and Philips Electronics North America Corporation
register eligible circuits under the Semiconductor Chip Protection Act.
Copyright Philips Electronics North America Corporation 1995
All rights reserved. Printed in U.S.A.
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