Datasheet 74ABT652AN, 74ABT652ADB, 74ABT652AD Datasheet (Philips)

Philips Semiconductors Product specification

74ABT652AOctal transceiver/register, non-inverting (3-State)

1

1995 Apr 19 853-1614 15144

FEATURES

•Independent registers for A and B buses

•Multiplexed real-time and stored data

•3-State outputs

•Live insertion/extraction permitted

•Power-up 3-State

•Power-up reset

•Output capability: +64mA/–32mA

•Latch-up protection exceeds 500mA per Jedec JC40.2 Std 17

•ESD protection exceeds 2000 V per MIL STD 883 Method 3015

and 200 V per Machine Model

DESCRIPTION

The 74ABT652A high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.

The 74ABT652A transceiver/register consists of bus transceiver
circuits with 3-State outputs, D-type flip-flops, and control circuitry
arranged for multiplexed transmission of data directly from the input
bus or the internal registers. Data on the A or B bus will be clocked
into the registers as the appropriate clock pin goes High. Output
Enable (OEAB, OEBA

) and Select (SAB, SBA) pins are provided for

bus management.

QUICK REFERENCE DATA

SYMBOL PARAMETER

CONDITIONS

T

amb

= 25°C; GND = 0V

TYPICAL UNIT

t

PLH

t

PHL

Propagation delay
CPBA to An or CPAB to Bn

CL = 50pF; VCC = 5V

3.7

4.3

ns

C

IN

Input capacitance VI = 0V or V

CC

4 pF

C

I/O

I/O capacitance

Outputs disabled;
V

O

= 0V or V

CC

7 pF

I

CCZ

Total supply current Outputs disabled; VCC =5.5V 110 µA

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE ORDER CODE DRAWING NUMBER

24-pin plastic DIP –40°C to +85°C 74ABT652AN SOT222-1
24-pin plastic SOL –40°C to +85°C 74ABT652AD SOT137-1
24-pin plastic SSOP Type II –40°C to +85°C 74ABT652ADB SOT340-1

24-pin plastic TSSOP Type I –40°C to +85°C 74ABT652APW SOT355-1

PIN CONFIGURATION

SA00094

CPAB

SAB

OEAB

A0
A1
A2
A3
A4
A5
A6
A7

GND

1
2
3
4
5
6
7
8

9
10
11
12

V

CC

CPBA
SBA
OEBA
B0
B1
B2
B3
B4
B5
B6
B713

14

15

16

17

18

19

20

21

22

23

24

PIN DESCRIPTION

PIN NUMBER SYMBOL FUNCTION

1, 23

CPAB /

CPBA

A to B clock input / B to A clock input

2, 22

SAB /

SBA

A to B select input / B to A select
input

3, 21

OEAB /

OEBA

A to B Output Enable input /
B to A Output Enable input
(active–Low)

4, 5, 6, 7,

8, 9, 10, 11

A0 – A7 Data inputs/outputs (A side)

20, 19, 18, 17,

16, 15, 14, 13

B0 – B7 Data inputs/outputs (B side)

12 GND Ground (0V)
24 V

CC

Positive supply voltage

Philips Semiconductors Product specification

74ABT652AOctal transceiver/register, non-inverting (3-State)

1995 Apr 19

2

LOGIC SYMBOL

23 CPBA
22 SBA

21OEBA

CPAB1

SAB2

SA00095

B0 B1 B2 B3 B4 B5 B6 B7

20 19 18 17 16 15 14 13

4 5 6 7 8 9 10 11

A0 A1 A2 A3 A4 A5 A6 A7

3OEAB

LOGIC SYMBOL (IEEE/IEC)

SA00096

21

3
23
22

1
2

4

5

6

7

8

9

10

11

EN1 [BA]
EN2 [AB]

C4

G7

C6

G5

20

19

18

17

16

15

14

13

1

1

5 4D

5

1

1

2

6D 7

1 7

FUNCTION TABLE

INPUTS DATA I/O

OEAB OEBA CPAB CPBA SAB SBA An Bn

OPERATING MODE

L
L

H
H

H or L↑H or L

↑

X
X

X
X

Input Input

Isolation

Store A and B data

X

H

H
H

↑
↑

H or L

↑

X
**

X
X

Input

Unspecified

output*

Store A, Hold B

Store A in both registers

L
L

X

L

H or L

↑

↑
↑

X
X

X**Unspecified

output*

Input

Hold A, Store B

Store B in both registers

L
L

L
L

X
X

X

H or L

X
X

L

H

Output Input

Real time B data to A bus

Stored B data to A bus

H
H

H
H

X

H or L

X
X

L
H

X
X

Input Output

Real time A data to B bus

Store A data to B bus

H L H or L H or L H H Output Output

Stored A data to B bus
Stored B data to A bus

H = High voltage level
L = Low voltage level
X = Don’t care
↑ = Low-to-High clock transition
* The data output function may be enabled or disabled by various signals at the OEBA

and OEAB inputs. Data input functions are always

enabled, i.e., data at the bus pins will be stored on every Low-to-High transition of the clock.

** If both Select controls (SAB and SBA) are Low, then clocks can occur simultaneously. If either Select control is High, the clocks must be

staggered in order to load both registers.

Philips Semiconductors Product specification

74ABT652AOctal transceiver/register, non-inverting (3-State)

1995 Apr 19

3

The following examples demonstrate the four fundamental
bus-management functions that can be performed with the
74ABT652A.

The select pins determine whether data is stored or transferred
through the device in real time.

The output enable pins determine the direction of the data flow.

}

REAL TIME BUS TRANSFER

BUS B TO BUS A

OEABOEBA

CPABCPBA SAB SBA

L L X X X L

}

REAL TIME BUS TRANSFER

BUS A TO BUS B

OEABOEBA

CPABCPBA SAB SBA

H H X X L X

}

STORAGE FROM

A, B, OR A AND B

OEABOEBA

CPABCPBA SAB SBA

X H ↑ X X X
L X X ↑ X X
L H ↑ ↑ X X

}

TRANSFER STORED DATA

TO A OR B

OEABOEBA

CPABCPBA SAB SBA

H L H | L H | L H H

SA00097

A B A B A B A B

Philips Semiconductors Product specification

74ABT652AOctal transceiver/register, non-inverting (3-State)

1995 Apr 19

4

LOGIC DIAGRAM

1D

C1

Q

19
18
17
16
15
14
13

B1
B2
B3
B4
B5
B6
B7

5
6
7
8

9
10
11

A1
A2
A3
A4
A5
A6
A7

DETAIL A X 7

OEBA

OEAB

CPBA

SBA

CPAB

SAB

21

3

23

22

1

2

20

B0

1D

C1

Q

4

A0

1of 8 Channels

SA00098

PARAMETER CONDITIONS RATING UNIT

V

CC

DC supply voltage –0.5 to +7.0 V

I

IK

DC input diode current VI < 0 –18 mA

V

I

DC input voltage

3

–1.2 to +7.0 V

I

OK

DC output diode current VO < 0 –50 mA

V

OUT

DC output voltage

3

output in Off or High state –0.5 to +5.5 V

I

OUT

DC output current output in Low state 128 mA

T

stg

Storage temperature range –65 to 150 °C

NOTES:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .

2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.

3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

ABSOLUTE MAXIMUM RATINGS

SYMBOL

1, 2

Philips Semiconductors Product specification

74ABT652AOctal transceiver/register, non-inverting (3-State)

1995 Apr 19

5

RECOMMENDED OPERATING CONDITIONS

LIMITS

SYMBOL

PARAMETER

Min Max

UNIT

V

CC

DC supply voltage 4.5 5.5 V

V

I

Input voltage 0 V

CC

V

V

IH

High-level input voltage 2.0 V

V

IL

Low-level input voltage 0.8 V

I

OH

High-level output current –32 mA

I

OL

Low-level output current 64 mA
∆t/∆v Input transition rise or fall rate 0 10 ns/V
T

amb

Operating free-air temperature range –40 +85 °C

DC ELECTRICAL CHARACTERISTICS

LIMITS

SYMBOL PARAMETER TEST CONDITIONS T

amb

= +25°C

T

amb

= –40°C

to +85°C

UNIT

Min Typ Max Min Max

V

IK

Input clamp voltage VCC = 4.5V; IIK = –18mA –0.9 –1.2 –1.2 V

VCC = 4.5V; IOH = –3mA; VI = VIL or V

IH

2.5 3.0 2.5 V

V

OH

High–level output voltage VCC = 5.0V; IOH = –3mA; VI = VIL or V

IH

3.0 3.5 3.0 V

VCC = 4.5V; IOH = –32mA; VI = VIL or V

IH

2.0 2.4 2.0 V

V

OL

Low–level output voltage VCC = 4.5V; IOL = 64mA; VI = VIL or V

IH

0.3 0.55 0.55 V

V

RST

3

Power-up output low voltage VCC = 5.5V; IO = 1mA; VI = GND or V

CC

0.13 0.55 0.55 V

I

I

Input leakage Control pins VCC = 5.5V; VI = GND or 5.5V ±0.01 ±1.0 ±1.0 µA
current Data pins VCC = 5.5V; VI = GND or 5.5V ±5 ±100 ±100 µA

I

OFF

Power-off leakage current VCC = 0.0V; VO or VI ≤ 4.5V ±5.0 ±100 ±100 µA

IPU/I

PD

Power-up/down 3-State
output current

4

VCC = 2.1V; VO = 0.5V; VI = GND or V

CC

;

V

OE

= Don’t care; VOE = Don’t care

±5.0 ±50 ±50 µA

IIH + I

OZH

3–State output High current VCC = 5.5V; VO = 2.7V; VI = VIL or V

IH

5.0 50 50 µA

IIL + I

OZL

3–State output Low current VCC = 5.5V; VO = 0.5V; VI = VIL or V

IH

–5.0 –50 –50 µA

I

CEX

Output High leakage current VCC = 5.5V; VO = 5.5V; VI = GND or V

CC

5.0 50 50 µA

I

O

Output current

1, 5

VCC = 5.5V; VO = 2.5V –40 –65 –180 –40 –180 mA

I

CCH

VCC = 5.5V; Outputs High, VI = GND or V

CC

110 250 250 µA

I

CCL

Quiescent supply current VCC = 5.5V; Outputs Low, VI = GND or V

CC

20 30 30 mA

I

CCZ

VCC = 5.5V; Outputs 3-State;
V

I

= GND or V

CC

110 250 250 µA

∆I

CC

Additional supply current per
input pin

2

VCC = 5.5V; one input at 3.4V,
other inputs at V

CC

or GND; VCC = 5.5V

0.3 1.5 1.5 mA

NOTES:

1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

2. This is the increase in supply current for each input at 3.4V.

3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.

4. This parameter is valid for any V

CC

between 0V and 2.1V , with a transition time of up to 10msec. From VCC = 2.1V to VCC = 5V ± 10%, a

transition time of up to 100µsec is permitted.

5. This data sheet limit may vary among suppliers.

Philips Semiconductors Product specification

74ABT652AOctal transceiver/register, non-inverting (3-State)

1995 Apr 19

6

AC CHARACTERISTICS

GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω

LIMITS

SYMBOL PARAMETER WAVEFORM

T

amb

= +25oC

V

CC

= +5.0V

T

amb

= -40 to +85oC

V

CC

= +5.0V ±0.5V

UNIT

Min Typ Max Min Max

f

MAX

Maximum clock frequency 1 125 300 125 MHz

t

PLH

t

PHL

Propagation delay

CPAB to Bn or CPBA to An

1

2.2

1.7

3.7

4.3

5.1

5.1

2.2

1.7

5.6

5.6

ns

t

PLH

t

PHL

Propagation delay

An to Bn or Bn to An

2

1.5

1.5

3.0

3.6

4.3

4.6

1.5

1.5

4.8

5.4

ns

t

PLH

t

PHL

Propagation delay

SAB to Bn or SBA to An

3

1.5

1.5

3.5

4.2

5.1

5.2

1

1.5

1.5

6.5

5.9

ns

t

PZH

t

PZL

Output enable time

OEBA

to An

5
6

2
3

3.2

4.5

4.6

6.8

2
3

5.8

8.5

ns

t

PHZ

t

PLZ

Output disable time

OEBA

to An

5
6

1.5

1.5

3.9

2.9

4.7

1

3.8

1.5

1.5

5.3

1

4.1

ns

t

PZH

t

PZL

Output enable time

OEAB to Bn

5
6

2
3

3.5

4.7

6.1

6.5

2
3

6.5

7.4

ns

t

PHZ

t

PLZ

Output disable time

OEAB to Bn

5
6

1.5

1.5

3.8

3.0

4.6

1

4.4

1.5

1.5

5.5

5.1

ns

1. This data sheet limit may vary among suppliers.

AC SETUP REQUIREMENTS

GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω

LIMITS

SYMBOL PARAMETER WAVEFORM

T

amb

= +25oC

V

CC

= +5.0V

T

amb

= -40 to +85oC

V

CC

= +5.0V ±0.5V

UNIT

Min Typ Min Max

ts(H)
t

s

(L)

Setup time
An to CPAB, Bn to CPBA

4

3.0

3.0

0.7

0.7

3.0

3.0

ns

th(H)
t

h

(L)

Hold time
An to CPAB, Bn to CPBA

4

0.0

0.0

–0.5
–0.5

0.0

0.0

ns

tw(H)
t

w

(L)

Pulse width, High or Low
CPAB or CPBA

1

4.0

4.0

1.0

1.0

4.0

4.0

ns

Philips Semiconductors Product specification

74ABT652AOctal transceiver/register, non-inverting (3-State)

1995 Apr 19

7

AC WAVEFORMS

VM = 1.5V, VIN = GND to 3.0V

V

M

V

M

V

M

V

M

V

M

1/f

MAX

tw(H) tw(L)

t

PHL

t

PLH

CPBA or

CPAB

An or Bn

SA00087

Waveform 1. Propagation Delay, Clock Input to Output, Clock

Pulse Width, and Maximum Clock Frequency

V

M

t

PLH

t

PHL

V

M

V

M

V

M

Bn or An

An or Bn

SA00099

Waveform 2. Propagation Delay, An to Bn or Bn to An

V

M

t

PHL

t

PLH

V

M

V

M

V

M

SBA or SAB

An or Bn

SA00102

Waveform 3. Propagation Delay, SBA to An or SAB to Bn

V

M

An or Bn

V

M

V

M

V

M

V

MVM

CPBA or

CPAB

t

s

(H)

t

h

(H)

t

s

(L)

t

h

(L)

SA00090

NOTE: The shaded areas indicate when the input is permitted

to change for predictable output performance.

t

W

(L)

Waveform 4. Data Setup and Hold Times

OEBA

V

M

t

PZH

t

PHZ

0V

V

OH

–0.3V

V

M

V

M

An or Bn

OEAB

SA00100

Waveform 5. 3-State Output Enable Time to High Level and

Output Disable Time from High Level

t

PZL

t

PLZ

VOL +0.3V

V

M

V

M

V

M

OEBA

An or Bn

OEAB

SA00101

0V

Waveform 6. 3-State Output Enable Time to Low Level and

Output Disable Time from Low Level

Philips Semiconductors Product specification

74ABT652AOctal transceiver/register, non-inverting (3-State)

1995 Apr 19

8

TEST CIRCUIT AND WAVEFORM

PULSE

GENERATOR

R

T

V

IN

V

OUT

C

L

R

L

V

CC

R

L

7.0V

Test Circuit for 3-State Outputs

V

M

V

M

t

W

AMP (V)

NEGATIVE
PULSE

10% 10%

90%

90%

0V

V

M

V

M

t

W

AMP (V)

POSITIVE
PULSE

90% 90%

10%

10%

0V

t

THL

(tF)

t

TLH

(tR) t

THL

(tF)

t

TLH

(tR)

VM = 1.5V

Input Pulse Definition

DEFINITIONS

RL = Load resistor; see AC CHARACTERISTICS for value.
C

L

= Load capacitance includes jig and probe capacitance;

see AC CHARACTERISTICS for value.

R

T

= Termination resistance should be equal to Z

OUT

of

pulse generators.

INPUT PULSE REQUIREMENTS

FAMILY

Amplitude Rep. Rate t

W

t

R

t

F

74ABT 3.0V 1MHz 500ns 2.5ns 2.5ns

SWITCH POSITION

TEST SWITCH

t

PLZ

closed

t

PZL

closed

All other open

SA00012

D.U.T.